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CSD95485RWJ: CSD95485 BOOT to BOOT_R Stress Test and Waveform Check

Part Number: CSD95485RWJ

Hi TIer,

Could you help us to judgement the BOOT to BOOT_R exceed 7V risk? Thanks!

  • Hi,

    Thank you for reaching out.

    The first thing I would recommend is to check the measurement setup. Please use differential probe with the probing tips as close as possible to the BOOT and BOOTR pins. This can prevent most of the measurement noise to be included in the waveform.

    Most cases if we measure right at the pins, we can see much lower spikes  caused by switching noises. If we still see high spikes, we may need to find the noise source, and reduce the noises.

    Best,

    Qingquan

  • Dear Sir,

    thank you very much for you great support and updated my measurement setup and measure point. (Currently Rboot-Cboot is 2.2 with 0.22uF.)

    socpe is Tektronix DPO7104C and differetial is TDP1000_42V_1GHZ

    Does it change with the phase node waveform? add the snubber circuit on phase-gnd is ok?

  • Hello,

    Thank you for the information.

    The probe and tips are good enough. From what I saw, the spikes  were coupled from switching, so snubber might help. You can give it a try. You may also want to check the timing to see if the switching noise is from this power stage itself, or adjacent power stage next to it. So you can slow down the switching of the noisy source which probably will be more effective.

    Another thing you can try is to scratch some solder mask and move the probing spot closer to pins. The previous measurement points have relatively long and curved traces connecting to pins, which added extra parasitic inductance. 

    Best,

    Qingquan

  • Dear Sir,

    thanks for your great support and I have question about Cboot and Rboot location need you help.

    Do you have data to explain where the resistor location is better?

  • Hello,

    Usually we place the RBoot on the right side and connected to BOOTR pin, but I don't see if you place on the other side since it's in series with the capacitor.

    The key is to minimize the loop and place both C and R as close as possible to the pin to reduce the parasitic inductance. 

    Best,

    Qingquan

  • Dear Tang,

    thanks for your recommended! if place on left side whether effect performance? 

    John

  • Hi John,

    As I mentioned earlier, I don't see any issue but just didn't try on left side before. In most designs we placed on right side.

    Best,

    Qingquan