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TPS3890: TPS389030DSET keeps reset all the time

Part Number: TPS3890

there is 1pcs chip   TPS389030DSET, it is a reset chip, it works properly during PCBA function test, but when we assembled it into our optical module, the whole board did not work, after failure analysis, we found chip TPS389030DSET Vout keeps low all the time. we check its IV curve and Impedance between Pin2 and Pin6,  no abnormal was found.

  We suspected this chip was damaged by ESD since this chip is only allowed 750 CDM ESD but we found one fixture in our production line with 800V ESD, we would like to verify whether it is damaged by ESD, so we have questions, please help to answer, thanks a lot!

1) which kind of condition will lead to Pin 6 keeping low?

2) Whether ESD diodes of pin6 will lead to such failure?

3) Please help to explain the theory of Pin 6 keeping low, but IV and impedance between pin6 & 2 are both normal.

Thank you for your kind support.

  • Hi,

    Please see below the answers to your questions.

    1) which kind of condition will lead to Pin 6 keeping low?

    There are several factors that keep the output low.  Is the part powered up when you are observing the output of the TPS3890?  What is the voltage you are monitoring on the SENSE pin (pin #1)?  Is pin #3 held low when you are observing the part?  What about VDD?  

    2) Whether ESD diodes of pin6 will lead to such failure?

    There is a probability that the internal circuits are damaged because the pin experience an ESD event that is higher than what the pin is rated for.  We cannot guarantee the functionality of the part if the ESD voltage is above the ESD voltage limit.

    3) Please help to explain the theory of Pin 6 keeping low, but IV and impedance between pin6 & 2 are both normal.

    Pin 6 is an open-drain output which means the pin itself is connected to the drain of an NMOS transistor. As mentioned above, if pin 6 is low, the device is turned on because the SENSE voltage is below the voltage threshold or pin 3 is low.

    Can you tell me if this problem is the first time you have experienced with the TPS3890?  Is your application new?  Have you used the TPS3890 before on another application/ / project? 

    I hope I have answered your questions.  

    Ben 

  • sHi  Ben

        thank you for your quick responds, today we had a meeting to discuss this issue, please see my feedback, it is highly appreciated to get your feedback soon, thanks a lot!

    1) which kind of condition will lead to Pin 6 keeping low?

    There are several factors that keep the output low.  Is the part powered up when you are observing the output of the TPS3890?  What is the voltage you are monitoring on the SENSE pin (pin #1)?  Is pin #3 held low when you are observing the part?  What about VDD?  

    Fancy: we did monitor the output of TPS3890 when power on, we monitor pin #6 with 1V trigger level and piin #6 keeps low during power on.  We did not monitor Vsense, but we connect Pin #1 to Vdd and both Vdd and Vsense are always 3.3V, we test Vdd and Vsese several times and its voltage keep at 3,.3V.  we have conducted SWAP test, failure goes with the fail chip. .

    2) Whether ESD diodes of pin6 will lead to such failure?

    There is a probability that the internal circuits are damaged because the pin experience an ESD event that is higher than what the pin is rated for.  We cannot guarantee the functionality of the part if the ESD voltage is above the ESD voltage limit.

    3) Please help to explain the theory of Pin 6 keeping low, but IV and impedance between pin6 & 2 are both normal.

    Pin 6 is an open-drain output which means the pin itself is connected to the drain of an NMOS transistor. As mentioned above, if pin 6 is low, the device is turned on because the SENSE voltage is below the voltage threshold or pin 3 is low.

     

    Can you tell me if this problem is the first time you have experienced with the TPS3890?  Is your application new?  Have you used the TPS3890 before on another application/ / project? 

    fancy: it is not the first time we have experienced with TPS3890, we have used it in several projects, it works ok in other projects. And in this project, it worked in the first beginning, it pass our PCBA function test. After  it fail after we assembly this PCBA into our optical modules and run module level test , then it failed.

     

    there are another two questions from my team:

    1) we would like to test IV curve test  with Pin4 to all other pins, that is to say, we want to test IV curve of  pin4 to pin1, pin4 to pin2, pin4 to pin3, pin4 to pin 5, pin4 to pin6, would you  please help to provide the voltage and current limitation when we conduct IV curve between Pin4 to other 5 pins.

    2) we have conduct IV curve of pin2 to other 5 pins, there is no abnormal.  We want to confirm, if  there is no abnormal of IV curve, does it indicate the chip has low possibility to be damaged by ESD.

     

     

     

     

     

  •   I would like add something to qustions2, we want to confirm, if there is no abnormal of IV curve of all IO to ground and Vdd, does it indicate the chip has low possibility to be damaged by ESD?

  • Hi,

    1) we would like to test IV curve test  with Pin4 to all other pins, that is to say, we want to test IV curve of  pin4 to pin1, pin4 to pin2, pin4 to pin3, pin4 to pin 5, pin4 to pin6, would you  please help to provide the voltage and current limitation when we conduct IV curve between Pin4 to other 5 pins.

    Base on the datasheet specs, the max voltage on all the pins are 7V max.  See page 4.  If a IV curve test is being done, I would limit the current in the uA range as you increase the voltage on the pins.  Is the IV curve test being done with a curve tracer?

    2) we have conduct IV curve of pin2 to other 5 pins, there is no abnormal.  We want to confirm, if  there is no abnormal of IV curve, does it indicate the chip has low possibility to be damaged by ESD.

    The statement above is not true.  There can be slight damage internally from an ESD event that is above specification which can affect the performance of the IC.  Going above the ESD rating has caused this particular part to not function properly.  I cannot quantify the level of damage from this ESD event or what is the possibility of damage.  The only thing that I can say is that the ESD event has caused some kind of failure to the IC.

    Ben

  • Hi  Ben

       thank you for your quick responds, I would double confirm again, If I want to run IV curve between power pin(pin #4) and other 5 pins, can I set maxim current to 5uA?

    Yes, we have done IV curve tracer with all pins to  GND (pin 2), below is the IV curve trace for you reference.

  • Hi,

    Yes, you can set the maximum current to 5uA.  Can you try and measure the IV curve for pin 6 to GND?

    Ben