Original question:
How do I implement interlock protection using the UCC5304 in half-bridge applications?
What is interlock protection, and how is it implemented in a driver?
IGBTs and Silicon/SiC MOSFETs are critical to the operation of the system in which they operate, so it is important that they are protected. The devices are not only crucial for efficient operation; they are also one of the most costly components in a system. When devices are arranged in a half bridge, as shown in Figure 23, they cannot both switch on at the same time. Thus, dead time is used before the switches change states and both devices are turned off momentarily during the switching cycle. If the devices turn on at the same time, shoot-through will occur and cause a large current spike and potential failure. Shoot-through can occur in the event of an incorrect dead-time calculation that is too short, varying propagation times between drivers, or noise at the input. Interlock is a feature in gate drivers to prevent shoot-through. Logic circuitry combines the positive and negative inputs of a gate driver such that they can never be on at the same time. Think of it as an integrated dead-time feature that takes delays inherent to the driver into account. Even if there is an error in the user-programmed dead time, the driver interlock will not allow both outputs to turn on, thus preventing damage to the half-bridge switches. Interlock can be implemented for single-output or dual-channel drivers, as shown in Figures 24 and 25. In a dual-channel driver, the input channels are tied together internally; in single-output drivers, the inputs are tied together externally.
For the UCC5304 which has a single-input, some external logic is required to implement interlock. For half-bridge application, let's call the high-side logic input signal IN_Hi, and the low-side logic input signal IN_Lo. In order to provide interlock functionality, we need the following logic circuitry:
Please see this excellent document for more information on IGBT & SiC Gate Driver Fundamentals. Interlock is discussed on page 18.
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