SG3524: SG3524 Maximum Ratings for External Sync on Oscillatior Out pin

Derek,

Thanks for your inquiry and interest in TI here. I'll assign to an applications engineer on my team who will respond before Wednesday US time.

Regards,

John

Steve,

Though I don't know what circuitry exists inside this package, the capacitor connected to CT does not behave as if it discharges once a TTL threshold is crossed on OSC OUT.

Rather, CT discharge varies depending on the voltage/current into OSC OUT and the pulse width.

We already provide more than 1mA to OSC OUT in order to bring its voltage up to 3.5V and properly reset the ramp, and the internal resistance decreases as voltage applied increases which is the reason I asked for the maximum specs on this pin. Normally, when I see resistance drop as more voltage is applied I assume that we ran into some sort of overcurrent protection. Here is some data on this pin:

The reason we are asking for more detailed specs is because our PWM signals change depending on the width and amplitude of OSC OUT pulses.

In the first screenshot, a 330ns 4.64V pulse at OSC OUT drops the voltage of CT to 770mV.

330ns 4V6.tiff

In the second screenshot the voltage is decreased but remains above 3.5V. The same 330ns 3.56V pulse at OSC OUT only drops the voltage of CT to 1.14V. I had to change the scale on this screenshot because the voltage ramp was shifted upward.

330ns 3V6.tiff

In the third screenshot, the pulse width at OSC OUT is increased. A 680ns pulse pf 3.56V drops the voltage of CT to 740mV.

680ns 3V6.tiff

If you could please find the specs for this pin, so we know how much current this pin can safely handle or have a better idea of the circuitry it is driving, I would appreciate it.

Regards,

Derek

Hi Derek,

I will check on the pin impedance and current rating. In the meantime, please make sure the width of the external SYNC pulse is less than the CT discharge time as measured when no SYNC is applied (50% is a good target). What are the values of RT and CT and please show the circuit, if possible?

Steve M

Hi Steve,

Per the attached circuit:

• The value of RT is 10k and the value of CT is ~1000pF. A small amount of parasitic capacitance is added to CT because these parts are in a socketed breadboard for evaluation.
• To keep the voltage on OSC OUT from exceeding spec, we form a divider between our 15.0V pulses *will be 12V in production* and the internal resistance of the OSC OUT pin with R35 (R_OSC_OUT).
• The duration of the pulse is determined by R34 (RD) and C30 (CD).

With R35 disconnected so that no SYNC pulses are given to OSC OUT, there is a 332ns pulse on OSC OUT when measured midpoint to midpoint on the OSC OUT waveform and its amplitude is 3.4V.

This is the behavior of CT after the positive edge of the pulse that is generated by the SG3524:

• CT starts discharging 40ns after the OSC OUT pulse has reached its maximum level.
• CT discharges with a fairly linear 23.5V/us slope for 124ns until reaching 840mV.
• CT continues to discharge with what appears to be an exponential decay for an additional 352ns until reaching its lowest amplitude, 720mV.
• CT recharges.

Behavior with no external SYNC pulse:

While I would like to make the SYNC pulses we feed into OSC OUT less than the discharge time of CT, all attempts to do so have been unsuccessful. In fact, the RC delay that determines the SYNC pulse width we feed to OSC OUT (made by RD and CD) was originally around ~60ns and we created it through the propagation delay of a logic gate but we needed a longer delay to reset the SG3524 without exceeding 3.5V on OSC OUT.

When we feed a narrow SYNC pulse into OSC OUT,  CT does not discharge completely. In the following screenshot we create a 4V pulse on OSC OUT with a width of ~140ns midpoint to midpoint. It does not cause a complete discharge, and CT continues to charge until the pulse generated by the SG3524 causes a complete discharge of CT as expected.

Since the rate of discharge depends on the width and amplitude of the pulse we apply to OSC OUT I look forward to learning the acceptable values.

Derek