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LM5069: Could you help me check the if LM5069 design is ok?

Part Number: LM5069

Hi team,

Attached files is our designing. Do you think if the design is ok? I have below 3 question need to check.

1. In the files, we can see "Minimum Power Limit to Ensure Vsns > 5mV (PLIM,MIN)" need 120W. But customer need that Power Limit target <=50W because they worry about the MOSFET will be broken when work in 120W. Do you think if it is ok?

2. If the power Limit target =50W,  in the files, we can see the Calculated RPWR=15.63K.  But when I use the Calculation formula in datasheet, like below.  VDS=VINmax=60V, Rsns is 2.5m. The result is 7K, which is different with 15.63K. Do you know why?

3. In the customer SCH, like below, they design RPWR=10K. And Timer capacitance =690nf. they product 200pcs board. And They found 2pcs board have problem. The issue is that the input current is smaller. We can see the waveform as below. Pic1 is abnormal waveform and Pic2 is normal waveform. The Yellow one is input current waveform, 100mv/A.

When customer change the RPWR=10K to RPWR=15K, the 2 board work.  We don't know if we have deal with it and are not sure if have other Potential issue.

Do you  have any suggestions?

Thanks! 

Pic1:

Pic2:

LM5069_Design_Calculator_REV_C_jiaqi.xlsx