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TLV710-Q1: Short of TLV7103318 output in Jacinto7 EVM design

Part Number: TLV710-Q1


In the Jacinto7 EVM design, the 1.8V and 3.3V output of TLV7103318 are short with 0ohm resistors as shown in the figure below. And here is description that if we want to achieve 3.3V output, the EN1 and EN2 should be both set to high voltage level. But as I think, the 1.8V LDO will sink current while the 3.3V LDO will source current then. And there will be a circle current inside those two LDOs.

Since I don't know if the 1.8V LDO will sink current, I used the Pspice model to complete a simple simulation, as shown in the figure below.

The simulation result is as the waveform below. It can be seen that there's about 10A circle current inside those two LDOs. That result also makes me confused since the current limit spec on datasheet is just about several hundred mA.

Could you give some explanation on this? Is the issue caused my mistake in simulation or it can't be used like this? Since my customer is confused about this part of EVM design, please help to provide some explanation of this kind use of TLV7103318. Why could it be used like this or why couldn't it...



  • Hi Andrew,

    From the simulation you have shown, where are you probing the OUT2 current? The high input current could potentially be attributed to a faulty model because VOUT2 and VOUT1 are essentially 2 different points on the same line, the current flowing through both the points should be the same. 

    As for configuration on page 82 of Jacinto7 DRA829/TDA4VM Evaluation Module (EVM) Users Guide (Rev. A), that is called dynamic scaling. 

    The Dynamic Voltage Scaling with a Dual LDO App note goes into better detail, but essentially the 1.8V output stays on at all times and when the 3.3V output turns on, the 1.8V output goes high impedance. The reason there are no issues with using the LDO in this configuration is because the TLV10 does not have an internal pulldown loop or an active discharge.