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TPS62148: Questions regarding testing conditions and efficiency in light load region

Hiroyuki Asaga
Intellectual 1735 points
Part Number: TPS62148

Hello,

Would you kindly provide feedback on customer questions below:

(1) The data sheet states RθjA: 38.4 ℃. Under what conditions is this the value?

Since there was a link to SPRA953C in the data sheet, I presumed that it is based on the JEDEC standard (EIA / JESD51), but I could not find any clear material on the testing conditions.

Can you possibly provide me any material that describes these testing conditions?

 

 

(2) Customer is considering using device in in forced PWM mode at 1.25MHz.

In this case, the frequency of 1.25MHz is fixed. Is the understanding that the efficiency drops in the light load region correct?

Any help is greatly appreciated!

Thank you,

Hiro

  • 0
    TI__Mastermind 21765 points

    Hiro-san,

    1. I am trying to find more information on the theta-ja query.

    2. Yes, it is correct that efficiency will be lower in light-load region in FPWM than PFM/PWM.

    Thanks,

    Amod

  • 0 in reply to Amod Vaze
    TI__Mastermind 21765 points

    Hiro-san,

    It could take more than a week to get an answer on query 1 as the engineer is currently out of office. I can confirm that the number is for a JEDEC PCB only and it will vary significantly depending on your board configuration.

    Thanks,

    Amod

  • 0 in reply to Amod Vaze
    TI__Mastermind 21765 points

    Hiro-san,

    I got feedback from the thermal modeling team. These theta-JA value is extracted from simulations using a JEDEC standard 2s2p PCB.  For this package, it looks like the PCB would have included thermal vias. The testing conditions used in the simulation are defined by JEDEC standard JESD51-2.

    Thanks,

    Amod

  • 0 in reply to Amod Vaze
    TI__Intellectual 1735 points

    Hello Amod-san,

    Thank you very much for your informative reply.

    As you mentioned in your previous post, the theta-JA will varies significantly depending on the PCB configuration and customer will like to know more specifically about the test PCB conditions used with the thermal simulation for this device.

    Specifically, customer is interested in test PCB conditions such as the dimensions of the test board and copper layer thickness.

    Is there any additional information regarding this that you may be able to provide?

    Thank you,

    Hiro

  • 0 in reply to Hiroyuki Asaga
    TI__Mastermind 21765 points

    Hiro-san,

    You have contacted me offline about this with additional questions. The JEDEC standard documents should contain the test setup and also the board dimensions and copper thickess used on the test board. You can refer to JESD51-2, JESD51-7 and JESD51-12 on jedec.org.

    Thanks,

    Amod