Other Parts Discussed in Thread: LM5069
Dear TI support team,
for a high-power design, we use 2x parallel FETs on the LM5069 to transport the load current. Output capacitance is >2mF, so a dV/dt soft start becomes necessary.
We use the Excel spreadsheet kindly provided by you to figure out the SOA constraints on dV/dt startup.
As highlighted in various sources, using parallel FETs in the linear region might not balance the load evenly (tolerance + negative temperature coefficient of V_g,th). So, dV/dt startup might happen through only 1 of the 2 parallel FETs.
Question: When calculating SOA margin during start-up (line 86 in the spreadsheet), is it taken into account that the load might distribute unevenly between the different FETs?