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TPS7A84A: EN voltage higher than Vin risk

Feng Wu
Prodigy 300 points
Part Number: TPS7A84A

Hi Team,

     Customer want to use 2.5V Vin and 3.3V EN high voltage at TPS7A8401A. On datasheet, EN max spec = Vin at recommendation value and EN max= 6.5V at ABS value. So I want to know if EN voltage higher than Vin voltage, is any risk here? Could do you help to explain the internal structure between EN and Vin pin? Thanks! 

  • 0
    TI__Genius 13085 points

    Hi Feng,

    There is no risk for the use case of Ven>Vin, as confirmation below is the Abs Max table which shows no Vin dependency for Ven. 

  • 0 in reply to Kyle Van Renterghem
    TI__Prodigy 300 points

    Thanks for your reply, Kyle.

            There is another PG questions from my customer which needs to check with you. 

    1. the recommendation of PG pull-up resistor is 10k to 100k, if the pull-up resistor is over the range, what may be the main influence and risk? 

    2. when PG is pull-down status, what's the internal pull-down resistance? Because customer what to calculate the sink current of this pin and evaluate the risk.

             Very appreciate for you reply.

     

  • 0 in reply to Feng Wu
    TI__Genius 13085 points

    Hi Feng,

    See my comments to the questions below:

    1. the recommendation of PG pull-up resistor is 10k to 100k, if the pull-up resistor is over the range, what may be the main influence and risk? 

    If the PG pull-up resistor is too large, then depending on the value of the external PG pull up voltage the PG pin leakage current (1uA max) could cause enough drop through the pull-up resistor for the PG signal to falsely indicate a logic-low condition. 

    If the PG pull-up resistor is too small, then that current multiplied by the on-resistance (Rdson) of the internal pull-down FET could cause the PG signal to falsely indicate a logic-high condition. 

    2. when PG is pull-down status, what's the internal pull-down resistance? Because customer what to calculate the sink current of this pin and evaluate the risk.

    The pull-down resistance is equal to the Rdson of the internal FET used to connect the PG pin to GND to indicate a logic low condition. That FET's Rdson  is typically between 110 Ohm to 200 Ohm based on the PG voltage vs PG Current Sink graphs in the datasheet (see below).

    We have been having constant struggle in production with kelvin probing on the device with 165um(post-reflow) ball size.  Probe mark shift and inconsistent Kelvin connection happen after running wafers in production for a while.
     

    These issues will happen on probing on 150um ball for sure and possibly even worse.