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TPS62148: GND plane on layer 2 of the TPS62148EVM-034

Part Number: TPS62148

We are currently using the TPS62148 in our design and we are trying to keep as much as possible of the corresponding Evaluation Module layout. The layout is documented in TI TPS62148 Evaluation Module User's Guide (SLVUBE9) and I have also obtained the actual gerber files.

Both sources indicate there are GND plane employed as follows:

  • on the Top Layer           (electric layer 1)     - all GND vias and component pads inside the GND plane perimeter (including IN and OUT connector header GND pins)  are connected to this plane
  • on the Internal Layer 1 (electric layer 2)     - only the three GND vias under the IC are connected to this layer; all other GND vias as well as the through hole GND pins of the IN and OUT connector headers are NOT connected to this plane
  • on the Internal Layer 2 (electric layer 3)     - all GND vias and component pads inside the GND plane perimeter (including IN and OUT connector header GND pins)  are connected to this plane
  • on the Bottom Layer     (electric layer 4)     - all GND vias and component pads inside the GND plane perimeter (including IN and OUT connector header GND pins)  are connected to this plane

So the curious and odd thing, which I do not understand, is the configuration on  Internal Layer 1 (electric layer 2): why most of the GND vias, as well as the through hole GND pins of the IN and OUT connectors are not also connected to the GND plane on this layer? Is there any particular reason for this?

Best regards,

Cristian