LM4132-Q1: Maximum output voltage when disable

Takahiro Saito

Part Number: LM4132-Q1

Hi team,

My customer asked me the maximum voltage at VREF pin when disable.

Does your team have such a data? I think VREF pin becomes Hi-Z, not low. So, I think there is no such a data. But, I appreciate if you could check if you have such a data.

Regards,

Saito

over 3 years ago

0 Marcoo Z over 3 years ago

TI__Mastermind 19500 points

Hi Saito,

We do not have this type of data available. As you mentioned the LM4132-Q1 goes into high-z when the input is off because the output stage is not powered.

The main connection to GND will be R1+R2 from the functional block diagram in 7-2. If Vout>Vin there can be leakage through Q1 and it does not have any internal reverse current protection circuitry. We do not have the value of when this will happen.

What is the cause of the VOUT > 0V during shutdown?

0 Takahiro Saito over 3 years ago in reply to Marcoo Z

TI__Expert 5365 points

Hi Marcoo-san,

I just answerd it to customer based on your reply.

I will ask you again when I need further asistance.

Regards,

Saito

0 Ajay Padgaonkar over 3 years ago in reply to Takahiro Saito

TI__Intellectual 1695 points

Saito-san,

Since this thread was closed, feel free to open a new one if more questions result after you consult the customer.

Thank you very much and good luck.

Regards,

ajay

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LM4132-Q1: Maximum output voltage when disable