Hello,
I want to implement the following configuration and thanks to ti technical team, I could find the answer of my questions. There is one more point that I would like to know your opinion about. In the following circuit, having in mind the suggestion given by ti team, I decided to select CA1 and CA2 values around 10-20 times larger than my gate charge with two 100nF capacitors in parallel in order to filter the high frequency noises. Paying attention in the configuration, we could see there is another capacitor which decouples the VDAA from VSSA. Among the following options which one do you suggest for Cd? (please consider that I am using CA1 and CA2 and their parallel 100nF capacitors in all of the cases)
1. Removing the Cd because the capacitors CA1 and CA2 are already present.
2. Using only a smaller capacitor (100nF) to ensure the high frequency noise mitigation.
3. only using a large capacitor (10 to 20 times larger than gate charge) without a smaller capacitor (100nF) in parallel
4. I must use a large capacitor (10 to 20 times larger than gate charge) in parallel with a 100nF capacitor to mitigate the high frequency noise effect.
Another question that I have is why do you use an Roff in series with a diode? I know this is implemented in order to decrease only the turn-off resistance, but why do we want to reduce the gate resistor size during the turn-off?
Best regards,
Hossein.
