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UCC21540-Q1: UCC21540-Q1

Part Number: UCC21540-Q1

Hello,

I want to implement the following configuration and thanks to ti technical team, I could find the answer of my questions. There is one more point that I would like to know your opinion about. In the following circuit, having in mind the suggestion given by ti team, I decided to select CA1 and CA2 values around 10-20 times larger than my gate charge with two 100nF capacitors in parallel in order to filter the high frequency noises. Paying attention in the configuration, we could see there is another capacitor which decouples the VDAA from VSSA. Among the following options which one do you suggest for Cd? (please consider that I am using CA1 and CA2 and their parallel 100nF capacitors in all of the cases)

1.  Removing the Cd because the capacitors CA1 and CA2 are already present.

2. Using only a smaller capacitor (100nF) to ensure the high frequency noise mitigation.

3. only using a large capacitor (10 to 20 times larger than gate charge) without a smaller capacitor (100nF) in parallel 

4. I must use a large capacitor (10 to 20 times larger than gate charge) in parallel with a 100nF capacitor to mitigate the high frequency noise effect.

Another question that I have is why do you use an Roff in series with a diode? I know this is implemented in order to decrease only the turn-off resistance, but why do we want to reduce the gate resistor size during the turn-off?

Best regards,

Hossein.

  • Hello Hossein,

    Our expert on this device is out of the office at the moment. He will respond to your questions shortly.

    Regards,

  • Hello again,

    I would like to mention another point. Your colleague provided me a link

    At which CA1 and CA2 are replaced with two 0.1 uF capacitors only to mitigate the high frequency noise. While instead of using two large capacitors for CA1 and CA2, Cd is considered as two parallel 4.7 uF for decoupling purpose and one parallel 0.1uF for noise mitigation. Please let me know whether this configuration works in my circuit case also. Then it would be perfect for my PCB layout.

    Best regards,

    Hossein.

  • Hello Richard,

    Thank you for informing me.

    Best regards,

    Hossein.

  • Hi Hossein,

    The Cd is mostly dependent on your power supply structure. We would need to know if you are using a flyback, or push/pull, or other topology, plus what the ripple of your supply is. However the linked reference design would very likely work just fine in your application, just check the that your power supply topology is similar to the one in the reference design.  

    "Cd is considered as two parallel 4.7 uF for decoupling purpose and one parallel 0.1uF for noise mitigation"

    The two 4.7nF capacitors you see here in parallel are output filtering capacitors for the power supply, not decoupling capacitors. Depending on your power supply type you might not need them. But having them there would be safe. 

    Your last question, 

    "Another question that I have is why do you use an Roff in series with a diode? I know this is implemented in order to decrease only the turn-off resistance, but why do we want to reduce the gate resistor size during the turn-off?"

    These two resistors control the speed the your FET turn on or off. You might want to turn the FET on slowly and off quickly, which will reduce the risk of shoot-through(where both FETs in the half-bridge turn on at the same time). Making Ron bigger than Roff, will make the FET turn on slower and turn off faster. Essentially you don't want one FET to turn on while another hasn't turned off yet. 

    Regards,

    Krystian

  • Hello Krystian,

    Thank you so much for the helpful information. Because I have several MOSFETs, I have to supply the drivers by the means of isolated DC/DC unregulated converters like SFTNO2M-12.

    Do you suggest the use of two or one 4.7 uF capacitor considering that my driver is supplied by this converter?

    Best regards,

    Hossein.

  • Hi Hossein,

    If you check the datasheet of SFTNO2M-12, it has 75mVp-p ripple voltage with 47uF+0.1uF capacitor (note 2), so your Cd selection should be based on the requirement of SFTNO2M-12.  

    Regards,

    Gangyao