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TPS3803-Q1: Reset output and Voltage monitor threshold

Ryotaro Fukui
Intellectual 2345 points
Part Number: TPS3803-Q1
Other Parts Discussed in Thread: TPS3899

Hello team,

My customer has a question about TPS38x-Q1: How reset output behaves and how its related with monitoring voltage.

Please see the graph in the attached file. Questions are 3 below:

  • Is it correct that the monitoring voltage needs to be below the threshold for >10% or >5% time period of set delay time in order to operate reset release?
  • Is there no particular time period stated for exceeding the monitoring voltage threshold? Is it simply canceled if it exceeds the Delay setting time, and is not canceled if it is not exceeded?
  • If the voltage above and below the monitoring voltage threshold is repeated, is the understanding in following cases true?(From p.2 of slides)

I am not familiar with this field and the question text may be strange, but if you have any comments about it, please contact me.

Best Regards,

Ryotaro FukuiTPS38x-Q1_ResetOutput&VoltageMonitorThreshold.pptx

  • 0
    TI__Mastermind 28365 points

    Hi Fukui-san,

    Please see graph below.  I believe the graph below will explain the undervoltage timing questions you may have and it also applies for the overvoltage case as well.  The graph is from TPS3899 but the waveform applies to your questions.  

    • Is it correct that the monitoring voltage needs to be below the threshold for >10% or >5% time period of set delay time in order to operate reset release?

      That is not correct.  The monitored voltage needs to be below the set threshold for longer than the programmed time period set by CTS capacitor in order to have reset signal be asserted.

    • Is there no particular time period stated for exceeding the monitoring voltage threshold? Is it simply canceled if it exceeds the Delay setting time, and is not canceled if it is not exceeded?

      Again, this is not correct.  If the monitored voltage does not exceed the programmed time period set by CTS, the reset signal will not be asserted.  The monitored voltage must exceed the programmed time period in order for reset to be asserted.  

    • If the voltage above and below the monitoring voltage threshold is repeated, is the understanding in following cases true?(From p.2 of slides)

    Just like the undervoltage cases that I mentioned above, for overvoltage conditions, the same condition applies where the monitored voltage needs to be above the set threshold for longer than the programmed time period set by the CTS capacitor in order for the reset signal to be asserted.

    Please feel free to reach out to me if you have any other questions.  

    Ben