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TPS7A66-Q1: Enable / disable timing specs

Part Number: TPS7A66-Q1

Hello, Could you advise how long the enable needs to be pulsed low to trigger a reset of the LDO?
Also, what is the delay between EN falling from 3.3V -> 0V and the LDO shutting off the output.  

Thank you!

  • Hi Alan, 

    The EN is controlling the on/off states of the LDO. The PG power reset is monitoring the output rail and it will trip when the output (the internal reference) drops 90% of the norminal output. 

    Internally there is no active discharging path for the output when disabling the LDO. When disabling, the output ramping down time will be primarily decided by the load at the LDO. There is no direct relationship between EN falling to PG trip. 

    Regards, 
    Jason Song