Other Parts Discussed in Thread: , SN74LVC1T45, SN74AXC1T45
Hi Mr./Mrs.,
We follow LMZ34002EVM-001 Evaluation Module design with a level shifter(DCX144EH-7) at the INH / UVLO pin. We try to control LMZ34002 Enable/Disable by this pin. When the input signal of INH / UVLO (EVB TP7)=5V, LMZ34002 output is Enable, while when the signal of INH / UVLO (EVB TP7)=3.3V, LMZ34002 output is Disable. Because the intput signal of INH / UVLO in our design comes from the FPGA and the signal is 3.3V max, can we just bypass the level shifter (DCX144EH-7), then using two resistors divde the INH / UVLO signal 3.3V to 1V for example, to control LMZ34002 Enable/Disable?
ps.The VIN of LMZ34002 is 5V and A_OUT=-3V. If the input signal of INH / UVLO is 1V, VINH should be 1V-(-3V)=4V under the Absolute Maximum Rating of INH/UVLO?