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BQ24232 footprint - DRC errors in pcb editor

Other Parts Discussed in Thread: BQ24232


i'm using BQ24232 in my project. When i place this component in orcad pcb editor, DRC errors are generated (I attach an image of my problem - DRC are identified in yellow circles).

How i can resolve these DRC errors without waived them?


  • Hi Patricia,

    Can you tell us more about the DRC errors? I'm not familiar (more familiar with Altium which is what we use). 

  • Hi Anthony,
    the DRC (Design Rule Check) errors are generated if your design does not match with the project's rules. In my case, i'm using default orcad rules.
    I have downloaded BQ24232 footprint by ultralibrarian and when i place manually the components in my pcb board, a DRC error is generated. Specifically, the error reports:

    Constraint Name: Thru Pin to SMD Pin Spacing

    DRC Marker Location: (14.9825 0.3140)

    Required Value: 0.0127 CM

    Actual Value: OVERLAP

    Constraint Source: DEFAULT

    Constraint Source Type: NET SPACING CONSTRAINTS

    Element 1: Pin "U34.17 (0)"

    Element 2: Pin "U34.21 (Dummy Net)"

    and there is one error for each of the four internal pin of the footprint.

    Then, i don't understand why there are these internal pins (that seems to be Thru Pin) when the component has a VQFN package.


  • Hi Patrizia,

    Please ensure that your clearance between polygons is 0.635mm and clearance is 0.2mm. If possible also ensure that pad to pad clearances are ignored within a footprint. 

    The internal pins on the thermal pad are vias. This is to allow the thermal pad to provide an effective thermal contact between the IC and the PCB. 

  • Thank you very much Anthony. Now I have not DRC errors.