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TPS543620: Ramp and Power On Delay Timing

Part Number: TPS543620


On regulator startup, my customer is looking for BP5 LDO startup time and power on delay timing. Assuming R mode 1.78K +/-1% is used, what is the min/max of the ramp + turn on delay time?



  • Hi Russell,

    Anthony will feedback to you soon.



  • Hi Russell,

    I am looking into this but I will need to wait for some input from our design team to help answer. I believe we have not characterized this parameter with measurements and we will only be able to give numbers based on simulation data.


  • Hi Russell,

    Here are the details we can provide from design. Unfortunately it may not be as straight forward was you might hope but I hope this will be enough to satisfy the need here. With 12 V input, 1 µF capacitance at BP5 and 11.8-kΩ RFSEL (1 MHz), the expected min/max time from EN high to switching is 660µs/760µs. A 1 µF capacitance was used in the simulation to account for typical derating of a 2.2 µF cap. Of this delay time, the time it takes to charge up the 1 µF capacitance to the point the internal logic signal indicates the voltage is ok is 110 µs. This time will vary linearly with the actual BP5 capacitance and based on the data I suggest using +30%/-20% variation in this startup time across process and temperature. So for example a 2.2 µF cap results in 190 µs to 320 µs start up time for the LDO.

    Another detail is the power on delay related to the FSEL resistor detection will vary depending on the setting. To detect the resistor, the FSEL pin steps through current and a comparator looks at the voltage. The first step in current is for the 2.2 MHz setting and it cycles downwards to the 500 kHz setting. Once it detects the setting, it skips the remaining settings. So a 2.2 MHz fsw will have slightly lower power on delay. Each step lasts for 25 µs.  So for example, with the 2.2 MHz setting this takes 25 µs, with the 1000 kHz setting this takes 75 µs and with the 500 kHz this would take 125 µs. I do not have details on how these 25 µs steps vary with process and temperature. However the variation should not impact the total delay time significantly as the total delay time with a fixed FSEL setting only had a 100 µs range. The difference in delay time with different FSEL settings is much more significant.

    The MODE detection does not have the same change in delay as the FSEL detection between different settings.


  • Got it.  So you are saying 660us/760us min/max across process & temp in the above conditions, And that is from EN_high to... 90% Vout?

    Thank you as always Anthony!

  • Hi Russell,

    Those numbers are from EN_high to the beginning of the soft-start ramp. The SS ramp time needs to be added to it. Sounds like the min/max of the 0.5 ms soft-start might also be needed?