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UCD90160A: UV_WARN or OV_WARN asserting GPIO irregularly

Part Number: UCD90160A

Team, I am having a design issue relating to the UCD90160ARGCT Voltage Monitor/Sequencer.

 

Some details:

 

I have a monitored input on MON13 (+12.0V).  

The resistor divider used at the input of MON13 is Rtop = 4.99K / Rbot = 1.0K (Vout Scale set to 0.166).

I have set the under-voltage WARN and over voltage-WARN to +/- 12.5%.  I have configured GPIO14 to assert low when either the UV_WARN or OV_WARN is detected. 

 

When I slowly lower the 12V supply (MON 13), the GPIO asserts as expected.

 

When I quickly remove the 12V supply (MON13), the GPIO may or may not assert at all.  And when it does assert, it is at a significantly lower voltage than expected.  The decay time is roughly 6V/mS.

 

I am power-cycling the unit while it monitors the 12V input rail.  The 3.3V rail powering the UCD90160ARGCT is stable throughout most of the decay.  Significantly longer than when the GPIO should assert.

  • Hi

    The UV_WARN is only reported:

    1. The rail's internal state is set to ON which means that the ON/OFF_CONFIG of the rail is met to turn on and the sequencing on dependencies are all met.

    2. The voltage of the rail has been above the POWER_GOOD threshold and then drops below UV_WARNING

    The ADC is running at 400us interval to sample voltage. The assertion of the GPO is running at 100us interval which assumes no delay settings. So there could be 500us delay from voltage below UV_WARNING to GPO asserted. 

    Hope this helps.

    Regards

    Yihe

  • I did consider the sampling rate.  I don’t think it explains what I see. 

    If I measure from when the supply decays to the UV_WARN  point of 10.5V to the GPIO assertion (if it does assert), I get around 1.25mS – 3.0mS.   

    The GPIO signal asserts as expected, repeatedly when I slowly ramp the 12V down.

    I noticed that the power_good indicator for this supply behaves reliably and as expected.  It asserts with every power cycle unlike the UV_WARN.  Is there a case where the power_good can mask the UV_WARN output.  For example, during a very quick ramp down of the monitored voltage?

  • Hello

    Please provide the project file and waveforms of both fast and slow ramp down cases. 

    Regards

    Yihe

  • Hi

    The UV_WARNING detection is much slower than the UV_FAULT or POWER_GOOD detection.

    The UV_WARNING is done at 400us per channel while UV_FAULT/POWER_GOOD is at 400us for all configured channels.

    So the worst case for the UV_WARNING detection is NUM_CONFIGURED_CHANNEL*400us. if you have 10 rail configured, it may takes up to 4ms to detect UV_WARNING.  If during this 4ms time, the target rail was asked to shutdown by other rails, there would be no UV_WARNING for the target rail.

    Is the target rail set as fault shutdown slaves of other rails?

    Having a project file will speed up?

    Regards

    Yihe

  • this rail is not set to shutdown any other rails.  But I believe your description matches what I am seeing.  I can qualify the GPIO output I have with the POWER_GOOD and I think I will be all set.  Thanks for your help on this!