Hi,
Please review our LMR14006XDDCR (U13) placement and layout for EMI integrity.
Attached are the schematic and layout.
Thank you,
Bob
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Hi,
Please review our LMR14006XDDCR (U13) placement and layout for EMI integrity.
Attached are the schematic and layout.
Thank you,
Bob
Bob,
Looks pretty good! A small optimization could be to reduce the SW surface area. You can do this by moving C45 southeast, and slide the inductor closer to the IC. Move D26 to the right as well (C42 can move to the right a bit to make space).
Replace C59 with a smaller package (less inductance) and swap positions with C47 to reduce the current path loop for C59.
Also make sure the VOUT FB path does not get too close to SW under the inductor to help noise immunity.
-Sam
Bob,
One more thing, VIN is a large plane on the top layer. If this can go on a mid-layer with GND on either side, you will reduce radiated noise from SW ring showing up on VIN. That's the last of my suggestions :)
-Sam
Bob,
Looks great! A few notes:
-Sam