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TPS650250: How to increse the ramp time of LDO1 and LDO2

Part Number: TPS650250


I am using TPS650250 to power my ARTIX-7 FPGA XC7A50T-2CPG236C. 

Attached is the power tree used. And power estimation of ARTIX-7

As per xilinx datasheet minimum ramp time for all power rails should be 0.2ms. Can you please let me know the ramp time for LDO1 and LDO2