TPS650250: How to increse the ramp time of LDO1 and LDO2

Shifali N

Expert 2040 points

Part Number: TPS650250

Hi,

I am using TPS650250 to power my ARTIX-7 FPGA XC7A50T-2CPG236C.

Attached is the power tree used. And power estimation of ARTIX-7

As per xilinx datasheet minimum ramp time for all power rails should be 0.2ms. Can you please let me know the ramp time for LDO1 and LDO2

0 Emily Kong1 over 3 years ago

Hi Shifali,

Your post is being reviewed and a response will be provided shortly.

0 Emily Kong1 over 3 years ago

Hi Shifali,

I believe you have two open threads on this device. I will close this thread and continue this conversation at the following thread:

0 Shifali N over 3 years ago in reply to Emily Kong1

Expert 2040 points

Hi Emily,

I am okay with it

Power management forum