What is a typical failure mode of the PTV05010WH when the input voltage (specified as 5.5VDC max) applied to the POL is driven to 12VDC?
The POL is used on a qualification board testing one of our new processors with was involved in a failure.
The upstream power source providing 5.0VDC to the PTV05010WH failed sending 12VDC to V(IN) of the PTV05010WH.
The PTV05010WH appears to have fed 12VDC through to the output at least for a short duration prior to catastrophically failing.
The overvoltage condition on the load side destroyed the dual gate oxide transistors within the power planes of our DUT.
In order to confirm the root cause of the failure, I am attempting to document with authority each failure mode of devices within the failure path.
I am looking for a viable failure mode confirmation for the PTV05010WH that when exposed to an input voltage significantly exceeding the maximum V(IN) specification, one possible failure mode of the POL is that V(IN) appears at V(OUT) for at least a short duration prior to catastrophic failure.