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UCC2806: 50% Duty Cycle Operation

Darren (FAE)
Expert 5483 points
Part Number: UCC2806
Other Parts Discussed in Thread: UCC3806

I have a customer wanted to use the UCC2806M device in a HV application where the output is 1/2 the input voltage.
This is for a design they need a prototype PCB done by end of this month, so it is pretty high-priority.

To do this, they want to fix the switching frequency to have a 50% duty cycle.

The Datasheet (p6) mentions: 
AOUT and BOUT: AOUT and BOUT provide alternating high current gate drive for the external MOSFETs. Duty cycle can be varied from 0% to 50% where minimum dead time is a function of CT. Both outputs use MOS transistor switches with inherent anti-parallel body diodes to clamp voltage swings to the supply rails, allowing operation without the use of clamp diodes.

But the UCC3806 BiCMOS CURRENT MODE CONTROL IC Application Notes states:

The two UCC3806 alternating outputs consist of totem-pole MOSFET pairs. Duty cycle may be varied from 0 to 98% where minimum dead time is determined by the timing capacitor value. Both outputs use MOS transistor switches with inherent anti parallel body diodes to clamp voltage swings to the supply rails. This may allow operation without the use of clamp Schottky diodes on each gate drive as recommended with all bipolar ICs. Drive currents of ±500mA peak with rise and fall times of 65ns are typical performance specifications

Assuming the duty-cycle can be fixed at 50%, how would this be done?
(If the duty-cycle limit is 50%, then would this be as simple as pulling the error amplifiers INV pin to GND, forcing max duty-cycle?)

Assuming the duty-cycle can be set to 50%, what is the variation max/min over process and temp?

Regards,
Darren

  • 0
    TI__Mastermind 27325 points

    Hi Darren,

    UCCx806 is a push-pull PWM controller that is 2x 50% duty cycle limited. I apologize for the confusion here but it seems that some app notes, such as the one you referenced, refer to the duty cycle as “0 to 98%” while the data sheet correctly refers to “0 to 50%” in the context of AOUT and BOUT. The 0 to 98% makes sense if we are talking about the transformer duty cycle (combined AOUT+BOUT) which I assume was the meaning in the app note. For your customer who wants VOUT=VIN/2, you could pull INV LOW and command max duty cycle – this would be open loop, no regulation. Does VOUT have to change with changing VIN such that VOUT always equals VIN/2? If not, how about regulating a primary AUX winding (VCC) and allowing the secondary to cross-regulate? This could help with component temp/tolerance variations?

    Regards,

    Steve M

  • 0 in reply to Steven Mappus1
    TI__Expert 5483 points

    Hi Steve,

    Could you clarify for me what the duty-cycle variation over process/temp would be when INV is pulled to GND? I can't imagine it would be a perfect 50.0000% duty cycle over process/temp.

    The design doesn't need the output to track the input, but for this particular application they desire current to be able to flow from the output to the input, whenever the output voltage is larger than the input. (They are planning on an open-loop design)

    Also, they are using a separate input supply to provide VCC, so won't have an AUX winding for VCC in this design.

    Are there any other thoughts you might have on this? (This is a HV application, where VIN would be in the several-hundreds of volts range, and VOUT would be 1/2 this, or around 300Vdc)

  • 0 in reply to Darren (FAE)
    TI__Mastermind 27325 points

    Darren,

    Yes, of course the duty cycle will not be perfect 50.0000%, the oscillator frequency is varying by ±10.5%, but duty cycle should scale with oscillator variance. I believe any measurable duty cycle variation will be attributed to external factors, such as dead time as a percent of frequency (measurable duty cycle loss right off the bat), gate drive delay, rise/fall times of whatever the load (MOSFET) is seen by OUTA, OUTB. Use an NPO CT capacitor and 1% or better RT capacitor and call is a loss of 1-2%.

    Regards,

    Steve M