If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Part Number: LM5146-Q1

Please refer to the picture attached. For the Regulator LM5146-Q1, the formula for finding the Rlim resistor is mentioned in the datasheet. In the numerator, the minimum current through the low side MOSFET M2 is taken i.e. Iout-delta(iL)/2 .  But since, this circuitry is used for overcurrent protection, we feel that the maximum current i.e.  Iout+delta(iL)/2 should come instead of Iout-delta(iL)/2 in the numerator. I request you to please explain the logic behind  Iout-delta(iL)/2 term in the numerator, because even during the OFF cycle, the maximum current in the below transistor would be  Iout+delta(iL)/2

• Hello, this is a valley current limit, hence the ripple current is subtracted from the DC current level.

• Can you please tell the logic behind subtracting the ripple current from the DC current level? The maximum current would be Iout+delta(iL)/2 only right, because we are doing overcurrent protection. If we are using Iout-delta(iL)/2, then that would mean undercurrent protection is getting implemented. Please correct me if I am wrong.

• Hi Ankit,

Yes, the peak current will be Iout + deltaI/2, but the valley current is detected during the low-side FET conduction interval (hence the ripple is subtracted from that standpoint).

Note that if the peak current is detected, it would be during the high-side FET on time and differential sensing (Vin - SW) would be required. The description is in the datasheet.

Regards,

Tim

• ok....so can you please explain what is the use of checking the lowermost current value.....and comparing it with the Reference voltage? Like what purpose does valley current sensing solves?

• Ankit,

The inductor ripple current is typically 30-40% of full-load current, so the valley is 15-20% below the DC level. This is a common technique to implement current limit with advantages as follows:

1. It prevents current limit runaway as the high-side FET will not turn on until the valley current decays to the threshold.
2. It allows sensing using the low-side FET or a sense resistor, so the resultant signal is ground referenced.
3. It avoids noise issues related to short PWM on times, current spikes related to diode reverse recovery current, level shifting, etc. when sensing using the high-side FET.

Regards,

Tim