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UCC28782: How to adjust the negative exciting current

Part Number: UCC28782

Negative exciting current is larger than expected.
Reducing the RDM resistance had no effect. Is there a possible cause?
The FETs used are: What is the proper negative excitation current for SJ_MOS?

QL: IPA65R225C7
QH: IPD70R360

thank you

wavefome.pdf

  • Hello User4243385,

    Thank you for your interest in the UCC28782 ACF controller.
    The -1A peak negative current that you show in the waveform is not unreasonable for the 264Vac input level. It may take considerable current to ring a high capacitance down to zero V.

    Im- is calculated according to Equation 29 (page 67 of the datasheet) and is proportional to Vbulk. So its amplitude will be highest at high line.
    It is also proportional to sqrt(Csw), so the total effective switched node capacitance includes estimations of the Coss of each MOSFET plus other circuit contributors.
    These are calculated using the UCC28782 Design Calculator Tool  https://www.ti.com/lit/zip/sluraz0 

    RDM resistance is intended to program the PWMH on-time range to the nominal set-point determined by Equation 11.  An internal tuning loop will automatically adjust PWMH on-time to obtain the correct level of Im- for the given line and load conditions.  There is a tuning range to allow for component tolerance variations, so changing RDM slightly will have no effect. Changing RDM drastically will eventually affect Im-, but will also prevent the tuner from operating properly and can result in loss of ZVS and subsequent hard-switching. 
    Please restore the RDM resistance to the value recommended by the Design Tool. 

    Regards,

    Ulrich

  • thank you for your answer.

    We understand that the negative current increases at the high line.

    I think the fall of L_Vds is too steep.
    The fall time of a test board using GaN is about 200 nsec, but is it possible to adjust it to the same extent with SJ_MOS?

    I thought that the internal tuning loop would adjust the negative current so that the fall time would be the same even if the switch capacitance was different. Is this a mistake?

  • Hello User4243385,

    There is no mistake.  The tuning loop does not adjust the negative current to achieve any particular fall time. 
    It adjusts the current to achieve "lossless" ring down to zero-voltage at the turn-off of the high-side FET.

    The steep fall time is a consequence of the non-linear Coss of the FETs which comprise most of the switched-node capacitance.
    A GaN-FET has much lower Coss than a Si-FET, but both have a much higher capacitance when Vds is low and much lower capacitance when Vds is high. So while the switched node voltage is high, the negative current drives a fast dV/dt until the Vds approaches low voltage.  At that point the non-linear Coss increases drastically at the same time that the ringing current is beginning to reduce.  So the Vds finally approaches zero volts at a very low dV/dt.    

    If the switched node capacitance (mostly Coss) was a fixed, linear capacitance, the Vds waveform would be sinusoidal in shape.  
    However, the sharp non-linear inflection of capacitance makes the Vds shape steep at first followed by shallow at the end.
    The tuner adjusts Ineg to ring the voltage just to about zero, not much "below" zero and not much above zero.
    It uses the voltage monitored at the SWS pin to maintain the proper current level to achieve that point.  

    Regards,
    Ulrich