Other Parts Discussed in Thread: BQ25798
Hi
The customer design the schematic and then supply voltage to VBUS find the SYS output voltage unstable.
Attached the schematic and waveform for your reference.
3323.BQ25792.pdf1830.waveform.xlsx
If use battery(Vbat>3.5V) or VBUS + Vbat (Vbat>3.5V,REG00 default setting) ,SYS output voltage is stable.
Why only supply VBUS the output voltage unstable?
Waiting for your reply.
Thanks
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