Other Parts Discussed in Thread: BQ25798
The customer design the schematic and then supply voltage to VBUS find the SYS output voltage unstable.
Attached the schematic and waveform for your reference.
If use battery(Vbat＞3.5V) or VBUS + Vbat (Vbat＞3.5V,REG00 default setting) ,SYS output voltage is stable.
Why only supply VBUS the output voltage unstable?
Waiting for your reply.