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TPS23754: frequency sync and PW limitations

Ohad Mizrahi79
Prodigy 50 points
Part Number: TPS23754

We are using the TPS23754  as POE application in one of our designs.

During the design phase, We used the TPS23754EVM_420 as reference designs.

/cfs-file/__key/communityserver-discussions-components-files/196/POE_2D00_PS.pdf

The POE output was set to 6.2V @ 3 amp max and we have to synchronize the POE to 650kHz.

The max Switching frequency described in the datasheet is 278 kHz with RFRS = 68.1 kΩ , while higher frequencies are described for different RFRS values( see below).

Since in our design RFRS = 69.8kΩ the free-running Switching frequency is set to 245kHz. 

We would like to confirm that our design supports the desired sync freq of 650kHz (without changing RFRS).

Looking in the datasheet we found that "The converter may be synchronized to a frequency above its maximum free-running frequency by applying short AC-coupled pulses into the FRS pin"

Furthermore, we didn't found any limitation on the F sync max pulse width.

Please advise if we can use 650kHz sync freq or that we would have to change RFRS or to use a lower sync freq.

Thanks,

Ohad

 

  • 0
    TI__Mastermind 21320 points

    Hey Ohad,

    It is possible to have the TPS23754 switch at 650kHz with the AC coupled pulses to the FRS pin. However, The TPS23754EVM-420 would need to be completely redesigned. The transformer inductance is spec'd for 250kHz, so it would be inaccurate. Plus, you probably need a lower inductance to be able to keep up with the switching frequency. This leads to higher peak currents so you need new FETs. Additionally, the FETs we chose are probably too slow to switch at 650kHz, so you'd need new FETs. Same with the pulse transformer and the gate drive circuit on the secondary. Additionally the feedback control loop is completely designed around the switching frequency, so all of that would need to be redesigned too. The output inductor would also need to change. 

    All in all, you are basically starting over. We do not have any reference designs at this frequency, so we cannot give you any reference material. 

    Typically, the switching frequency is increased in order to decrease the magnetic component size. If you are not requiring that, I'd strongly suggest sticking to a design that has been built and verified in the lab with test results. 

    If this post answers your question, please indicate so by marking this thread as resolved. Thank you.

     

    Regards, 

     

    Michael P.

    Applications Engineer

    Texas Instruments 

  • 0
    Prodigy 50 points

    Hi Michael,


    Thank you for your detailed answer.
    I have 2 questions:

    1. what will happen to the current design when providing 625KHz sync, will it damage the TPS23754 and or the FETs, or won't synchronize at all?
    2. Is it possible to synchronize the current design to 312.5kHz instead 625KHz?  Please specify the limitation on  F sync max pulse width under those conditions.

    Thanks,

    Ohad

     

     

  • 0 in reply to Ohad Mizrahi79
    TI__Mastermind 21320 points

    Ohad,

    My answer remains the same. It will probably not work because none of the components are designed to work at those frequencies. We do not spec limitations on the DCDC design over a range of frequencies because most DCDC designs are not intended to work over a frequency range so large. 

    However, the TPS23754 can operate at those frequencies with a timing sync and you can design a new DCDC to work at those frequencies. 

    If this post answers your question, please indicate so by marking this thread as resolved. Thank you.

     

    Regards, 

     

    Michael P.

    Applications Engineer

    Texas Instruments 

  • 0 in reply to Michael Pahl
    Prodigy 50 points

    Hi Michael,

    Thank you once again for your fast answer.

    Sorry but I didn't understand may I  sync the current design to 312.5kHz ?  or that I must sync it to a lower freq.

    Can you please specify the maximum Sync Freq + min&max Sync Freq pulse width allowed  for this design?

    Thanks,

    Ohad

     

  • 0 in reply to Ohad Mizrahi79
    TI__Mastermind 21320 points

    This design is intended for 250kHz. 

    If this post answers your question, please indicate so by marking this thread as resolved. Thank you.

     

    Regards, 

     

    Michael P.

    Applications Engineer

    Texas Instruments