Other Parts Discussed in Thread: LP87702
How long does it take for LP87702's Power GOOD to activate?
Is there a chance to shorten it?
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PG0_RISE_DELAY and PG1_RISE_DELAY fields in PG0_CTRL (0x18) and PG1_CTRL (0x1A) registers control the debounce delay of the powergood. From the picture it looks like the bit is set to 1 meaning 11 ms delay. Writing the bit to 0 shortens the delay to around 7 µs.
The default reset value depends on the used OTP. For catalog LP87702K-Q1 and LP87702D-Q1 solutions the OTP defaults can be found from the following document.
PGx_RISE_DELAY is set to 11 ms for both of the devices.
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