This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM5175: DC charger stability between buck-boost mode

Part Number: LM5175
Other Parts Discussed in Thread: LM5176,

Hi,

I'm designing DC charger using LM5175 IC, specs:

Vin: 10-16V

Vout: 14V

Switching Freq: 256k Hz

We encounter an issue below

When the DC charger start-up in boost mode it will deliver about 20A, then when we increase input voltage to push the DC charger work under buck mode, it will drop to 16-17A. However, when we decrease input voltage to force it to work under boost mode, it won’t do 20A again.

Is there something relate to COMP and SLOPE control?

https://www.ti.com/tool/LM5175QUICKSTART-CALC

I had a look at TI cals sheet and work out phase margin is 11 degree and cross-over freq is 21.3k Hz.

Do you have any suggestion to select RC value for COMP pin?, e.g. what is the cross-over freq?

Thanks,

VT

  • Hello VT,

    In boost mode you need to make sure that you are well below the RHPZ frequency. The calculator gives this value in the compensation area. Normally you should set the crossover frequency at the lowest VIN maximum to 1/5 the RHPZ.

    The SLOPE capacitor is essential for the stability during transition between the modes. Please make this one as small as possible.

    In general I have to mention that the current capability in buck-boost is lower than in buck mode. The current capability of LM5176 is in buck-boost mode higher.

    Best regards,
    Brigitte

  • Thanks Brigitte for your reply. It was really helpful answer.

    I have another question about AGND and PGND. Technically, we should isolate these 2 GNDs and only join them at one point (near the VCC
    capacitor PGND connection, as recommendation from LM5175 specs). However, when I check LM5175 EVM, these 2 grounds are both connected together on a same plane.

    Are there any explanation for this?, which option should I go for when designing a layout. 

    We already had a production that using LM5175 IC and I have been connected these 2 GNDs on a same plane. It seems no problem at all. Are there any downsides if we are doing that? Or what are the benefits of isolating AGND and PGND and only join them at one point?

    Thanks,

    VT

  • Hello VT,

    On all 3 EVMs, AGND and PGND are separated and only connected through the power pad of the IC, so this is the best connection you can use. If you are using a plane for both GNDs, AGND will be more noisy and noise can influence the regulation.

    Best regards,
    Brigitte

  • Hi Brigitte,

    Thanks for your prompt response.

    Yes, I had a look again on the EVM layout, it is separated. It is hard to tell when you only look at the EVM schematic as it doesn't really tell us that they are separated.

    Talking about the EVM layouts, I found that it is 6 layers board. There are 2 internal layers (mid-layer 1 & 4) that only connected to GND. Is there any reason for using 6 layers board?, e.g. improve EMI?

    We already have a design based on LM5175EVM-HP layout. We applied a same component orientation as an EVM board. However, we did combine the layers together in order to achieve a 4 layers PCB instead of 6. So my question is: will it have any impact on EMI? or any downsides? 

    I had a look through all an article about layout tips for four-switch buck-boost using LM5175 (e2e.ti.com/.../four-switch-buck-boost-layout-tip-no-4-routing-gate-drive-and-return-paths) and quite strictly followed those tips on the gate-drive signals and their return paths. Is there any that you could recommend for a high-power design layout using LM5175 in order to improve EMI?

  • Hello VT,

    If you followed all layout tips given in the 4 technical articles about 4-sw buck-boost converters, I think you are on the save side.

    In general for EMI, it is good practice to add gate resistors (to slow down switching if needed), add snubbers on the sync FETs in case they are needed and place small caps as close as possible to the power stage on the input and output. These shall be capacitive for the frequency of the switching noise, which you measure without them. All of these do not need to be populated for the first tests, but it is good to have some spaces to be able to place something if needed.

    I do not expect that a 4-layer design is heavily worse in EMI than a 6 layer design, but I did personally not measure it.

    Best regards,
    Brigitte