UCC21750: Gate Driver bias supply design

Dino,

Nam, Dino said:

1. Will adding series resistor(Red circle) like below cause other side effect?

You will have a slight reduction of the level of the DC level of the supply voltage, and therefore increase power consumption due to I^2R losses thru the supply-series resistors.

Nam, Dino said:

2. I think the series resistor on VDD and VEE line plays the similar role as Gate Resister. Is it right?

Not exactly, because of the function of the decoupling caps which can quickly source current in the initial burst directly to the IC pin. If you had no decoupling caps, or placed the series resistor between the decoupling caps and the driver supply pins, then yes it would be more or less equivalent to the effect of gate resistor. This is probably why there is less impact to turn on/ turn off speed.

Nam, Dino said:

 If yes, I think the switching time have to be slow but as you can see below waveform, we can see similar speed under without/with series resistor. please let me know your opinion on this.  

The plots are very small and can't zoom in. if you uploaded higher res images i could see more clearly. But from there it doesn't look like there is little effect on turn on on speed. I also am not exactly sure what the green / blue / pink waveforms are.

Having the series resistors in the supply is OK, but their chief function should NOT be to be used as extra gate resistors. They should be sized to have virtually no effect. If used, their only purpose should be to limit current in case of an IC failure which would short the supplies to ground and otherwise consume a ton of current. If the supply ICs has its own limiting function, then i wouldn't use the series resistors.

the VGS ringing is often caused by current injection thru miller cap of the device. High dv/dt at the switch node directly affects this per I=Cdv/dt relationship.

You can reduce ringing by multiple ways

* Reduce dv/dt of the switch node -> Increase the RG(OFF) of the high-side driver to reduce turn-off speed and thus reduce switch node dv/dt

These changes below require layout changes:

* Reduce the stray inductance at the gate as much as possible, including by

* adding Ferrite bead close to gate

* Placing gate resistors as close to the gates as possible.

* ensuring really good layout of the gate turnon / turn on paths.

* Place wide miller clamp trace directly to the gate, as close as possible.

* Boost miller clamp strength  with PNP booster circuit.

Main goal is to reduce the inductance, and ensure lowest impedance path to VEE as possible. You are technically increasing the impedance of path to VEE and thus reducing effectivenes of miller clamp by the series resistors.

I would recommend not to rely on the supply-series resistors for ringing reduction. I would suggest to increase RG(OFF), and you can try to add some clamping diodes as below, but layout should be made good as possible.

Miller clamp booster is effective in reducing ringing as well by increasing its strength.

Please let me know if any further questions. If this answers all your questions please let me know by pressing the green button.
Best

Dimitri

Hi Dino,

Thank you for reaching out. I will review and get back to you through email.

Best regards,

Andy Robles