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TLV740P: Voltage Drop Out Curve

Part Number: TLV740P

Hi Team,

Had a question about Figure 6-5 in the datasheet. What is the portion of the curve before linearity in dropout voltage vs. input voltage? It appears like the drop out is higher than the input voltage before the input reaches ~1.8V depending on temp. Does this imply the output will be regulating negative or am I reading this curve incorrectly?

Matt

  • Hi Matt,

                Thank you for your question. I believe that the Figure does not have the correct test conditions mentioned. The test condition is mentioned as IOUT = 1mA, but I am certain the graph was generated at full load condition. As input approaches 1.8V, at full load, the LDO is no longer able to supply the current and the Output becomes negative and the LDO is no longer regulating. I believe this results in the ESD diode turning on, leading to Vout ~ -700mV and hence the dropout (Vin - Vout) assuming a value of ~2.2V at Vin of 1.5V.

                 For Vout =1V, the Electrical characteristics table suggests that the maximum dropout is 1.3V for a load current of 300mA. We can hence deduce that the FET Drain -Source resistance, RDS ON, is ~4.4Ohms (1.3V/0.3A). For a load current of 1mA, the dropout required for regulation is around 5mV (4.4Ohms* 1mA). Therefore for Vout = 1V and IOUT = 1mA, the device would regulate just fine even for Vin = 1.5V. So, for this test condition (Vout = 1V, Iout = 1mA), the correct graph would continue to be linear for 1.5V ≤ Vin ≤ 2.5V as it is for Vin ≥2.5V. I hope this explanation was of help, if you have more questions please do not hesitate to get back to us. Thanks!

    Regards,                                                                                                                                                                                                                                                Srikanth