In the current situation, OUT1 and OUT2 have no waveform output. According to the operation of the data manual, power-on waits for the CLF to be low before sending the clock signal, but the CLF is always high. Even if the CLF signal is ignored, the sending clock signal OUT pin is still not output.
1. The ILIM setting voltage is 650mV.
2. The CLF voltage is 3.3v
3. CTRL voltage is 3.3v
4. CS voltage is 0V
5. ISET voltage is 1.85v
6. CLK setting frequency is 100k, 50% duty cycle.
7. Supplement: PVDD voltage is 10.6v.
Is there any special attention to this chip when designing the circuit? How to solve the problem of no drive signal output.
