UCD8220: The sending clock signal OUT pin is not output.

Lidong Yu

Part Number: UCD8220

In the current situation, OUT1 and OUT2 have no waveform output. According to the operation of the data manual, power-on waits for the CLF to be low before sending the clock signal, but the CLF is always high. Even if the CLF signal is ignored, the sending clock signal OUT pin is still not output.

1. The ILIM setting voltage is 650mV.

2. The CLF voltage is 3.3v

3. CTRL voltage is 3.3v

4. CS voltage is 0V

5. ISET voltage is 1.85v

6. CLK setting frequency is 100k, 50% duty cycle.

7. Supplement: PVDD voltage is 10.6v.

Is there any special attention to this chip when designing the circuit? How to solve the problem of no drive signal output.

over 3 years ago

0 John Stevens over 3 years ago

TI__Expert 7395 points

Lidong,

Apologies for the delay. We are trying to get hardware available to recreate what you are seeing. Can you email me at john.stevens@ti.com and we will support you through email?

Regards,

John

0 Hong Huang over 3 years ago in reply to John Stevens

TI__Guru 57385 points

Hi Lidong,

Based on the datasheet, it looks CTRL needs a pull-up in your circuit in order to clear CLF at start so to allow the IC to start to receive CLK.. Please refer to the reference design how to do pull-up on CTRL pin:

www.ti.com/.../slva578.pdf

If you still cannot get CLF low at initial start after you add pull-up to CTRL, let's continue through email as John suggested.

0 Hong Huang over 3 years ago in reply to Hong Huang

TI__Guru 57385 points

Please also refer to the datasheet 7.3.7 how to clear CLF.

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UCD8220: The sending clock signal OUT pin is not output.