Does the CTS signal is modeled in the spice model?
When I perform the a simulation I see that the RESET_B is asserted when the SENSE pin goes below VT- without the delay set by the capacitor on the CTS pin (300nF for minimum of 150msec).
The VCC in the simulation remain above 0.85V for the relevant time. I see the CTS pin charge as expected.
See image below.