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CSD18563Q5A: SOA measurement condition

Part Number: CSD18563Q5A


I went through a couple TI training videos and Blog posts from Brett Barr. He explained the concept very clearly and it was very helpful.
Brett mentioned that all the newer TI MOSFET SOA curve is based on data from measurement, but he didn't say anything about the measurement condition, and I couldn't find the information in the datasheet.

Would you please explain what the measurement condition is? The things I am looking for is cooling method, size and weight of copper, RthJA etc.

Take CSD18563Q5A as an example, from the SOA curve below, what is the DC line for a single pulse? Anything greater than 100ms? or it's a true DC power dissipation? For the DC curve, I found it difficult to believe that this device is capable of dissipating 30W continuously without adequate cooling. 

Thank you very much

  • Hello Hong,

    Thanks for your interest in TI FETs. You are correct. The DC line is actually 100ms pulse width. Testing was done to failure on a 2-sided DUT card with a minimum footprint similar to the picture below at the following Vds values: 3V, 5V, 8V, 12V, 20V, 30V, 45V & 60V. I believe the copper thickness is 1 oz.

    Best Regards,

    John Wallace

    TI FET Applications


  • Hi John,

    Thank you very much for the information. It is very helpful. Can you please put in a request for me to add this type of information to the datasheet in the future? I understand it won't happen overnight, but I am hoping it will be added eventually. There are some useful footnotes with PCB copper size and weight details for specifying  Drain current limit on the datasheet. Having similar information for SOA measurement condition on the datasheet makes a lot of sense.

    For CSD18563Q5A, was there any cooling involved during SOA measurement? I am asking because with bare minimum footprint, the datasheet calls out 125C/W RthJA, assuming ambient temperature is 25C, 30W (30V Vds and 1A Idrain) power dissipation will raise junction temperature to 3775C for 100ms. This is a mind boggling number. I feel like I am not understanding this right. are there other factors at play here? Like thermal capacitance? The thermal performance is not reaching the steady state because of thermal capacitance? or when the pulse duration is short enough, junction temperature is not just a function of thermal resistance and power dissipation?

    Thank you very much

  • Hi Hong,

    We'll look into the possibility of adding this information to the datasheets. I don't know if there is any forced airflow during SOA testing and I am checking with a colleague who was more closely involved in the SOA testing of these devices. It may be the thermal time constant from junction to ambient is relatively long in comparison to the pulse width. Using junction to case thermal impedance of 1.3C/W, the junction temperature rise from the case is 30W x 1.3C/W = 30.9C. To keep TJ < TJmax (150C), the case temperature can actually get up to 119C. Even then, the device probably will not fail if it is operated for a very short period of time at or even significantly above TJmax. In actual testing, the failure current was much higher than 1A. I guess I'm saying not to take RthetaJA as a "DC" value as there are time constants involved. This type of FET package is very effective getting heat from the silicon to the thermal pad on the case. A more rigorous approach would be to do a thermal simulation which is beyond the scope of this discussion. I'll update you when I get more information.

    Best Regards,