LM5069: Schematic review

Don Foong

Part Number: LM5069

Hi Team,

Pls help to review the attach LM5069 schematic. Thanks in advance for your help.

The 24V supply is from a 360W AC-DC converter and the current limit at J803 is 8A, the load capacitance (not shown in the schematic) is 1000uF max. Ambient temperature is 40 degC.

Attached is the LM5069_Design_Calculator tool filled with value base on the design requirements fyr. We notice the recommended Timer capacitance is 303nF. We will consider 330nF (the next standard value available), is this ok?

Look forward to your comment from the review. Thanks.

TF_LM5069_Design_Calculator_REV_C.xlsx

Regards,

Don

over 2 years ago

+1 Don Foong over 2 years ago

TI__Expert 4100 points

Attached IPD053N08 datasheet for reference.

Infineon-IPD053N08N3 NMOS 80V 5.3mOhm 90A.pdf

+1 Rakesh over 2 years ago in reply to Don Foong

TI__Guru* 95911 points

Hi Don,

Design looks fine. But I suggest to use dv/dt start for better SOA margin. Please refer attached updated sheet and let me know.

3617.TF_LM5069_Design_Calculator_REV_C.xlsx

Best Regards,

Rakesh

+1 Don Foong over 2 years ago in reply to Rakesh

TI__Expert 4100 points

Hi Rakesh,

Thanks for the help reviewing the schematic. We will suggest to customer to use dv/dt start circuit and share the updated calculation sheet.

Regards,

Don

0 Don Foong over 2 years ago

TI__Expert 4100 points

Hi Rakesh,

Notice in your proposed calculation sheet, the suggest Ctimer value is changed from ~303nF to 16nF after adding in the dV/dt circuit. Could you help to explain a little more regarding how does Ctimer and dV/dt circuit affect each other? Thanks again.

Regards,

Don

0 Rakesh over 2 years ago in reply to Don Foong

TI__Guru* 95911 points

Hi Don,

Please refer app note https://www.ti.com/lit/an/slva673a/slva673a.pdf . It covers in detail with examples on the purpose and benefit of dv/dt circuit.

Best Regards,

Rakesh

0 Don Foong over 2 years ago in reply to Don Foong

TI__Expert 4100 points

Hi Rakesh,

Thanks for sharing the file.

Is it true that dv/dt generally has shorter start-up time as the LM5069 startup with current limit instead of power limit?

How does the dv/dt circuit force LM5069 startup with current limit mode? I saw the gate voltage waveform is quite similar between power limit and dv/dt mode.

Thanks and regards,

Don

+1 Rakesh over 2 years ago in reply to Don Foong

TI__Guru* 95911 points

Hi Don,

Is it true that dv/dt generally has shorter start-up time as the LM5069 startup with current limit instead of power limit?

Rakesh-> It is opposite. Usually large start-up time in dv/dt mode to reduce the stress on the FET by lowering the inrush current.

How does the dv/dt circuit force LM5069 startup with current limit mode?

Rakesh->startup current in dv/dt mode will be Iout = Cout *dv/dt and the gate voltage in dvdt mode is Igate = Cgate *dv/dt

With higher Cgate, we can limit inrush current (Iout) to be lower than current limit Vsns/Rsense

I saw the gate voltage waveform is quite similar between power limit and dv/dt mode.

Rakesh-> which waveform are you pointing to ?

Best Regards,

Rakesh

+1 Don Foong over 2 years ago in reply to Rakesh

TI__Expert 4100 points

Hi Rakesh,

Pls disregards my question on gate voltage waveform, I notice there is differences. Vgate is linear in dv/dt mode (Figure 7. Start Up with ouptut dv/dt control). And is none linear in power limiting mode (Figure 2 - Start-up with only Power Limit).

Like to clarify one last point, from the calculation you have shared, the Target Fault Time is at 2mS. It should be >34mS right?

/cfs-file/__key/communityserver-discussions-components-files/196/3617.TF_5F00_LM5069_5F00_Design_5F00_Calculator_5F00_REV_5F00_C.xlsx

Thanks for all the support.

Regards,

Don

0 Rakesh over 2 years ago in reply to Don Foong

TI__Guru* 95911 points

Hi Don,

With dv/dt startup, fault timer setting becomes independent of power limit. So, we can use small fault timer period to increase the design SOA margin.

Best Regards,

Rakesh

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LM5069: Schematic review