https://e2e.ti.com/support/power-management-group/power-management/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1662657/tps25752a-datasheet-inconsistenciesThu, 09 Jul 2026 06:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:efa1e90a-4836-4c08-abc2-976b9dcb6defNikolas AthanasopoulosPart Number: TPS25752A Hello, Maybe I&#39;m missing something, but I&#39;m a bit confused by a few references in the datasheet. For example, in Section 8.4.2 (Layout Example), the example figures show components such as U11, U13, and J4, but I can&#39;t find these anywhere in the schematic shown in Figure 8-9. Also, Section 8.4.2.2.6 (PPEXT Gate Driver) refers to Figures 10-21 and 10-22, but those figures don&#39;t seem to exist anywhere in the datasheet. Am I looking at an outdated or incorrect revision of the document, or are these references simply errors? I&#39;d appreciate it if someone could clarify. Thanks!TPS25752ATest &amp; Measurementhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1659346/lmg5126-idelta-difference-observed-in-2-phase-operation/6410547Thu, 09 Jul 2026 06:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2f13bfec-9e78-42a4-8a88-b09f2c11b24ctoyoda daisukeHi Moritz, Thank you for your clarification. We added RCOMP, CCOMP, and CHF to the secondary device as well, while keeping the COMP pins connected between the primary and secondary devices as you suggested. As a result, the current-sharing mismatch improved significantly, and Idelta was reduced. Based on this result, we believe your recommendation was effective, and we plan to implement this configuration in the next PCB revision. However, the mismatch was not completely eliminated. We believe that the remaining mismatch may be related to additional factors such as PCB layout, routing asymmetry, or other parasitic effects. Due to the limitations of the current board revision, we were not able to investigate or modify those factors at this stage. Therefore, it seems that the current-sharing mismatch may be caused by multiple contributing factors, and the compensation network was one of them. I would also like to ask about the COMP pin. My understanding is that the COMP pin is the output of the error amplifier. In general, directly connecting error amplifier outputs together seems unusual, so I would like to confirm my understanding. For LMG5126, is it correct that the COMP pins are intentionally designed to be connected together during stacked multiphase operation and that this does not cause any issue? Also, when RCOMP, CCOMP, and CHF are implemented on both the primary and secondary devices, how should the effective compensation network be considered? Should the compensation components on both devices always have identical values? In addition, could you explain why adding the compensation network on the secondary side improved the current-sharing behavior? Finally, do you recommend re-optimizing the compensation values when using compensation networks on both devices, compared to a single-network implementation? Thank you for your support. Best regards, Toyodahttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1662232/lmg3422r030-internal-buck-boost-dc-dc-converter/6410548Thu, 09 Jul 2026 06:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bcdca880-3ea3-4949-a73b-5d6fec9e6acfKoshi NinomiyaHi Subhransu-sa, Servo drive frequency: fpwm=8kHz It is fixed frequency. PWM duty varies, minimum pulse width could be 5ns. Best Regards, Koshi Ninomiyahttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1662653/bq41z90-tenpower-inr21700-50xg-chemical-idThu, 09 Jul 2026 06:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:db9c851e-2d71-466f-9d7a-f98b229b188cAlihan SekerPart Number: BQ41Z90 Other Parts Discussed in Thread: BQSTUDIO Hello, I want to find a chemistry ID for the Tenpower INR21700 50XG cell by following the steps described in the SLVA725A document. According to the instructions, I first need to charge my battery pack, and then wait for a 2-hour relax period. After that, I need to discharge it at a C/10 rate until it reaches the minimum pack voltage. Following the discharge, another 5-hour relax period is required. Finally, I need to prepare the log file using GPCPackager in BQStudio and submit it. My questions are as follows: What happens if the relax time after charging is longer than it should be? Can I perform the discharge process at a C/5 rate? Or does it strictly have to be C/10? What happens if the relax time after discharging is longer than it should be? I would appreciate it if you could answer my questions.BQ41Z90bqStudioAerospace &amp; Defensehttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1660120/tps65994ad-tps65994-can-meet-2-type-c-ports-and-no-ec-wildcat-cpu-only/6410527Thu, 09 Jul 2026 06:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:93c5e3fd-c895-4d19-889b-9a46ce0cc7b3Yoro ChenHi Tommy, Should I contact you via e-mail? Thanks.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1661920/lm2596-buck-converter-controller/6410528Thu, 09 Jul 2026 06:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e672a7e3-09a2-4668-86c5-4f880ddfb6beSaeed ValipourHi Frank, As i said i need a buck controller not a converter. i have external mosfet and optocoupler.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1662203/bq79716b-q1-requested-for-documents-denied-request-by-ti/6410526Thu, 09 Jul 2026 06:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a18c7744-4666-42bd-b67e-c72964c3b1ebHrushikesh BorhadeHi Alex Findlay, My organization name is MAN bus and truck, India, we MTB already have NDA with TI. Our TI representative is Chen Ziqian. You can clarify if any NDA related doubt with him also I am requesting for access again. If any query, let me know. Thank and regards, Hrushikesh.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1662648/tusb1046a-dci-selection-of-components-supporting-dp-alternate-modeThu, 09 Jul 2026 06:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9ba3b451-fbac-4310-9d1f-077195f62eb6SATO KENJIPart Number: TUSB1046A-DCI Other Parts Discussed in Thread: TUSB1046EVM , TPS65987D I would like to implement video output via a USB Type-C connector, so I am currently selecting a USB PD control IC and a Redriver IC that support DP Alternate Mode. I am considering using the TUSB1046EVM for evaluation; is this board suitable for my application? This evaluation board uses the TPS65987D; please let me know the appropriate alternative part to use for a new design. Also, please recommend any other redriver ICs if available.TUSB1046A-DCITPS65987DTUSB1046EVMhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1661447/tps923650-multiple-errors-in-datasheet/6410520Thu, 09 Jul 2026 06:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0bdcf0d8-ce12-453a-a3dd-ffb3784e24ccLucia GaoDear Sir, The device don&#39;t support Webench. May I know your application and we can provide you the guidance. Thank you! BRs Luciahttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1660146/bq25798-tida-050047/6410514Thu, 09 Jul 2026 06:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8bdf805e-6199-40bb-aad6-658c0bdd3f6eYoav TzafrirThank you, this is helpful. Can I work in the TIDA-050047 reference design without the EEPROM (U5) at all (what will happen if I turn it off or completely remove U5 from the PCB)? Yoavhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1660264/tps26600-02evm-tps26600---no-output-current/6410508Thu, 09 Jul 2026 06:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:935a3fa8-9fb3-43b7-8b0f-2f6e42dfa668Bandaru HemanthI will also test it on my bench, by the end of tomorrow i will update you the results. thanks, Hemanth.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1662314/bq25890-usb-data-lines-connection-with-multiple-resources/6410507Thu, 09 Jul 2026 06:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ff6300a7-ee08-4c64-9234-3efd71396a24Mahammadirfan SaiyedHi Aaron, Thanks for your feedback. To avoid using an analog switch and make the MCU USB D+/D- pins we want to check that after power up at which time D+/D- lines go into the Hiz mode ? Is it Automatic or need any HW or SW register settings ? I have shared the below link where its been stated for other IC that after power up , Charger IC takes only 1s and then go to the Hiz mode. https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/883068/bq25616-how-to-split-usb-bus-d-d--to-connect-both-charger-and-cpu/3266770?tisearch=e2e-sitesearch&amp;keymatch=BQ25890EVM-664# Regards, Mahammadirfan Saiyedhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1661882/tps2492-unable-to-switch-on/6410503Thu, 09 Jul 2026 06:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:445c7e1d-4e0b-40a6-9aea-1afcddf48455Amrit JitHello, What&#39;s the Rsense value? There can be a load at start-up which could cause device to shut-down. Can you remove the L102 (series inductor) to isolate the downstream circuit and do the start-up. Thanks Amrithttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1660264/tps26600-02evm-tps26600---no-output-current/6410495Thu, 09 Jul 2026 06:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:43f50ec8-f714-4962-a9e5-0958725f83e1PHILIPPE FUMANERIHi, noted—I’ll set up a test rig for this measurement. Do you have any leads regarding this issue, which also occurs on this TI development board in a 48V configuration?https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1662169/lm5143-lm5143-related-circuit-design-and-pcb-layout-review/6410489Thu, 09 Jul 2026 06:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1e8c5409-dd34-4e8b-a380-90b599c04ff2Onkar BhakareHello Ash here is the link for the QuickStart - LM5143DESIGN-CALC Calculation tool | TI.com Thank you Regards Onkar Bhakarehttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1660263/lm51772-lm51772-does-not-produce-the-expected-output/6410484Thu, 09 Jul 2026 06:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b6c55b4a-e1ac-4c28-88f1-c7f5cc2783d7Steen HansenHi Hassan In my mind it should be working in boost mode with an input of 12V, so you tell me whats going on. What about the large gaps in activity on the SW1? This gap is also present on the SW2, as you can see. I will be of for 3 weeks of vacation from tomorrow, but I hope we can pick up when I am back. Br. Steen e2e.ti.com/.../SW2_2B00_Comp_2D00_1.ziphttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1662641/lmr51625-i-want-to-check-the-power-dissipation-and-estimate-the-junction-temperature-to-verify-whether-the-device-operates-within-the-acceptable-limits-at-a-60-c-ambientThu, 09 Jul 2026 06:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:30dfd69f-207a-41a8-b29d-7ade7bdf4d37Harshal PatilPart Number: LMR51625 for all ic please give me a its as per my requirement what is power disspationLMR51625https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1662639/lm51772-need-of-proper-pcb-layout-guidelinesThu, 09 Jul 2026 06:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cbb19f31-8e05-45ad-8fa5-0670d232c300Naveen R SPart Number: LM51772 Hello, I&#39;m designing a board using the LM51772 (4-switch buck-boost controller) and the datasheet&#39;s layout section doesn&#39;t cover PCB layout guidance in enough detail. Could you please provide detailed layout guidelines for this device? Application details: VIN range: 9V – 48V VOUT: 24V Max load current: 5A Topology: 4-switch Buck-Boost Ambient temperature: 30&#176;C Switching frequency: 0.613MHz I2C used: Yes Package: LM51772RHA, 40-pin QFN Design generated using TI&#39;s WEBENCH Power Designer: https://webench.ti.com/power-designer/switching-regulator/customize/11?VinMin=9&amp;VinMax=48&amp;O1V=24&amp;O1I=5&amp;base_pn=LM51772&amp;AppType=None&amp;Flavor=None&amp;op_TA=30&amp;origin=pf_panel&amp;lang_chosen=en-US&amp;optfactor=3&amp;Topology=Buck_Boost&amp;flavor=None&amp;VoltageOption=None Specifically, I&#39;d like guidance on: Power loop layout for the buck-side (Q1/Q2) and boost-side (Q3/Q4) switches — recommended component placement and loop area minimization. AGND/PGND separation and connection strategy around the thermal pad. Routing guidance for the current sense pins (ISNSP/ISNSN, CSA/CSB) relative to the switch nodes. Gate driver trace routing (HG/LG for both bridges) — any length-matching or spacing requirements. Any general best practices or an application note/reference layout beyond the LM51772EVM-HP. Is there a layout guideline document, application note, or annotated reference layout available for this device that covers these points? Thank you for your support.data storageLM51772LM51772EVM-HPhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1660028/ucc256403-question-about-isns-threshold-offset/6410473Thu, 09 Jul 2026 05:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3c1371c3-ead1-4dd3-a8e0-d45f4b422165Sougata NayakHi, I dont think this is a good way to conclude about the thresholds. But, What I can understand, At starting, if ISNS amplitude is low due to high switching frequency, noise may give false ZCS Flag and end up with restarting. Lets solve this issue in this way: In actual converter, Please increase both the capacitors at VCR to reduce startup frequency to avoid this issue. You can refer this document: ti.com/lit/an/slua836a/slua836a.pdf?ts=1762507794122&amp;ref_url=https%253A%252F%252Fwww.google.com%252F and the following section of the document: Regards, Sougatahttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1661411/ucc28950-relationship-between-the-sync-signal-and-the-output-sequence/6410469Thu, 09 Jul 2026 05:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:59f963ef-a053-4a10-8af2-b1a6a2cf27fcuser6304160Thank you for your explanation. I have one more question regarding synchronization. During the Burst OFF period, is the internal synchronization state (the phase relationship between the external SYNC signal and the internal PWM sequence) maintained? Or, when Burst mode ends, is the internal PWM sequence restarted from OUTB regardless of the current phase of the external SYNC signal? For example, if the external SYNC signal continues running during Burst OFF, does the controller continue tracking every falling edge of the SYNC signal, or is synchronization re-established only when switching resumes? I would like to know whether it is (a) or (b) from the waveform above. Regards,