This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • TI Thinks Resolved

TPS28225: PMP4123 design concept, rectifier cannot 3state/idle?

Prodigy 50 points

Replies: 1

Views: 390

Part Number: TPS28225

Dear polite inhabitants of this forum,

this time I'd like to ask something as a hobbyist :-)

I'm considering a "project" where I would use a symmetrical source of +/- 5V (relative to GND), to be fed from a 12V upstream PSU rail. I don't need anywhere near 120 Watt, but with respect to efficiency, I'm curiously eyeing some sync-rectified designs with an isolated secondary. Call it an academic interest at this stage :-)

I have noticed an interesting schematic in an article at that turns out to refer to a TI reference board called the PMP4123. It has a secondary-side MOSFET driver, synchronized across the isolation gap using low-latency capacitive couplers (isolators). At a first sight, this is so neat, nifty.

There's one thing that's caught my eye: I didn't understand how the LGATE driver in the TPS28225 knows when to switch off. Superficially and intuitively I thought the rectifier would go "UGATE, LGATE, idle" at lower than 100% load - and I was investigating in vain, in the TPS28225 datasheet, how it gets to know about the final "zero crossing" (at which moment it's time to go high-Z). There is nothing to indicate that the TPS28225 finds out somehow on its own, it doesn't have a current sensing input. There does seem to be a way to tri-state this MOSFET driver, if you provide it with an input level "inside the 3-state window", which spans about 50% of the input range, centered in the middle between GND and full log.1. The response time to the 3-state window is about 250 ns = not very fast, likely impractical for cycle-by-cycle rectifier shutoff. The ISO721 couplers can tristate their output, but only in response to their primary (transmitter) losing power. As long as the ISO721's primary part is powered, it works down to DC, but only in logic levels (it's digital, not analog). Plus, the PWM signal used as input to the isolators doesn't provide a 3rd state.

Note that there are no waveforms to be found around the aforementioned eetimes article or the reference design, to support my "UGATE, LGATE, idle" sequence. To me it was a mystery.

It only dawned on me when I looked up the UCC2897 datasheet. The catch is, that the PWM controller is "resonant". Resonant SMPS designs save power (a few per cent in efficiency) by starting the "inductor charging phase" just after the last "discharge phase" has reached a zero crossing. A resonant switcher does *not* waste a part of the duty cycle on idle time. Instead, it increases the switching frequency to back off with the output current.

And what's still unclear to me: does the PMP4123 design tolerate "down to zero" load levels? Or, does it require some minimal load on the output, corresponding to some upper limit on switching frequency?

The TPS28225 seems to be almost identical to chips from several competitors - in functionality, possibly pinout, and the typical application. This class of FET drivers is typically mentioned in the context of non-isolated buck converters, often multi-phase, for CPU VRM blocks etc. And I haven't found any application where the UGATE/LGATE duty cycle would "leave some slack of idle time" - i.e. it seems as if these chips are indeed intended for resonant designs...

Any comments welcome.

If I eventually build that isolated switcher, I will probably stick to some more conventional (and less efficient) constant-frequency design with variable duty cycle. And if I try synchronous rectification, I'll probably choose some "self-driven" secondary-side chip (PWM driver) using voltage and current sensing to determine the switching moments. Or I'll just find an off-the-shelf PCB-mount module :-)

  • Hi Frank,

    I am an HDP apps engineer and will help you out with all your questions. Thanks for your great question and info as well!

    check out "7.3.7 Dead-Time Control" of the DS

    The adaptive dead-time approach monitors the SWnode as an input and by sensing the output of driver going low prevents the other gate drive output going high until the first driver output falls below the specified threshold. (theres more about adaptive gate drive on as well)

    Also, the test results for PMP4123 no load are on page2 of the reference design results PDF - the no load condition of course results in 0% effiency and the the next available data point with a worthy efficency is at 2A.

    Please let me know if I can clarify or you have any more questions.


This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.