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[FAQ] TPS650830: How to Connect PMIC Pins for DDR3L, LPDDR4, LPDDR3, etc. Memory Types?

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Part Number: TPS650830

How to Connect PMIC Pins for DDR3L, LPDDR4, LPDDR3, etc. Memory Types?

Thanks!
Phil
--------------------------------------------------

For more information on Multi-Channel Power Management ICs: http://www.ti.com/pmic 

Find the right power solution for your processor or FPGA: www.ti.com/SoCPower

  • The TPS65083x supports several types of DDR memory: DDR3L, DDR4L, LPDDR3, LPDDR4, and DDR4RS.

    For LPDDR3:

    Connect VR4 output to the VDDQ, VDD2, and VDDCA rails or 1.2U (1.2V rail)
    Use a load switch to control the 1.8U rail or VDD1 rail.
    Suggested TPS22969 load switch from the 1.8A rail, (VR2 for TPS650830 & TPS650832 or VR5 for TPS650831)
    Enable the load switch with 1.8U_2.5U_POL signal or PGB pin.
    Monitor the 1.8U with the comparator VSB
    Connect ENB and ENVR4 to SLP_S4# to sequence the rails.

    For LPDDR4:

    Connect VR4 output to the VDDQ, VDD2, and VDDCA rails or 1.1U (1.1V rail)
    Use a discrete regulator to supply the 2.5U rail or VDD1 rail.
    Suggested TLV62080 regulator from the 3.3V rail
    Enable the regulator with 1.8U_2.5U_POL signal or PGB pin.
    Monitor the 2.5U with the comparator VSB using a resistor divider from the 2.5V to 1.8V
    Connect ENB and ENVR4 to SLP_S4# to sequence the rails.

    For DDR3L:

    Connect VR4 output to the VDDQ rails or 1.35U (1.35V rail)
    No 1.8 V or 2.5 V rail is needed for DDR3L memory so,
    Connect V1.8A to VSB to avoid Emergency Shutdown in the PMIC.
    PGB can be unused.

    Connect ENB and ENVR4 to SLP_S4# to sequence the rails.

    Thanks!
    Phil
    --------------------------------------------------

    For more information on Multi-Channel Power Management ICs: http://www.ti.com/pmic 

    Find the right power solution for your processor or FPGA: www.ti.com/SoCPower

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