Part Number: TPS65266
In our designing, we connect VIN1, VIN3,VINQ,EN1,EN2,EN3 together, but connect VIN2 to other circuit, which to ensure the LX2 will be powered after Lx1 and LX3.
It means, the EN2 will be powered before VIN2.
based on the testing, we found this circuit is working, and when VIN2 being powered, LX2 will be enabled after about 15ms, it is much longer than that between VIN1/VIN3 and LX1/Lx3( which is about 2ms).
Please help confirm whether this designing is normal and whether there is risk or not.
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In reply to Sam Zhang(MCP):
please refer below picture for the waveform, thanks
In reply to user5324035:
So do you mean, if we just adopt VIN2, the VIN2 can be powered after EN2, If we adopt VIN1~3, the VIN2 can not be powered after VINi,3, VEN 1,2,3, like our schematic, am I right?
So the schematic should be changed as below : powered VIN1~3, VEN1,VEN3 at firstly, and control the delay by powered the VEN2, am I right?
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