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Using the circuit in Figure 10 on Page 9 of the UC3823A spec sheet does not work on the bench or in simulation at 19.5 kHz unless replacing 39pF with 4700pF, 120 ohms with zero and 22 ohms with 16 ohms. Using Rt = 42.2K, this also violates the required 10 to 15% range requirement on how far below the input frequency the slave unit should be "programmed". The idea of programming the frequency of the slave unit is ambiguous, since the free running frequency is altered by the presence of the resistor to ground in series with the timing capacitor on pins 6 and 7, so it isn't clear which frequency is being "programmed" - with or without that resistor to ground. If I simulate at 400 kHz as shown in the spec sheet with Rt = 3.65K and Ct = 1nF for the master, and Rt = 4.11K, Ct = 1nF for the slave, I find that it just barely works. Sync is lost if Ct decreases by more than 2%. On the other hand, sync is OK for Ct increasing up to 70%, so in this case it makes sense to center Ct at 1.34nF, giving a +/-27% range of acceptable values. Has anyone else wrestled with this issue and worked out the spec sheet discrepancies? What are upper and lower limits on allowable peak voltage levels at pins 6 and 7?
I don' t think I can answer all your questions but let's see what I can do starting with the simple ones.
What are upper and lower limits on allowable peak voltage levels at pins 6 and 7? From the Absolute Maximum Table the limits are -0.3 V to 7 Volts for no damage. For operational limits I would keep things below 5 volts. The peak CT voltage (pin 6) generated by the IC in normal operation according to the data table is between 2.6 and 3 volts. The VZDC maximum is 1.4V (PWM comparator) so that puts the peak voltage self generated at 4.4 volts on the postive of the PWM comparator.
At 400 kHz with perfect Rt = 6.6k and Ct = 220 pF and 25 C the variations from IC to IC is 6.25%. With line and temperature added this is going to change to +/- 12.5%. This tolerance is set for 400 kHz if you add in variations for different frequencies there will be other changes. Lower frequencies usually imply large capacitors and this means the discharge current is higher. As an example the CT discharge transistor is probably one of the parts in the oscillator with the greatest variations so that is going to result in wider tolerances as the frequency decreases.
The minimum voltage for a "High" on the clock is 3..7 volts. This gives a 3.0 volt spike on the emitter of the NPN transistor in the sync circuit and with the resistors shown this should drive the voltage across the 22 ohm resistor up by just under 0.5 Volts. The recharge of the 39 pF cap will have a negative voltage developing across the 22 ohm resistor which will decrease the frequency. If the dv/dt of the 3 V on the emitter is not fast enough the charge will bleed off before the voltage is raised on the resistors. That would require the cap increase and possibly the resistors decrease which is what you are seeing.
At 18 kHz you are runnig the IC below the limits characterized for the part. See fig 2.
An alternate method of synchronization that you might want to consider is described in the attached link:
In this case you would be designing all the converters the same but choosing one as the master and then add the circuit to link them. They will run at the same frequency but there will be a phase difference. It is basically a voltage controlled phase locked loop.
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