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TPS 61151

Leo Werres
Prodigy 10 points
Other Parts Discussed in Thread: TPS61150, TPS61150A, TPS61151

Hi,

Using TPS61151 to drive 6 LED on one of the two rows. We have a strange effect. If we disconnect the display (the string of 6 LEDs) the chip blows up. I can measure a low resistance approx. 37 ohms between SW and GND in both directions instead of MOhms on a non defective chip.

In another design with the same circuit and a similar layout the chip works as it should. On a scope you can see that the output voltage rises to OVP smoothly and then it is set to a low output voltage when the OVP conditions are reached.

How can I prevent the chip from dying?

What causes the chip to die?

It looks like the OVP is not fast enough to protect the cicuit inside the chip. Are parasitic oscillations able to kill the chip when the output voltage without load reaches the over protection voltage?

Does it make sense to add a R-C network from SW to GND to damp the parasitic oscillations? Would you recomment this?

Is a TPS61150 a better solution?

Best regards

L. Werres

  • 0
    Prodigy 50 points

     I am having a similar problem with the TPS61150a.  I run 2 strings of 6 leds each.  Channel 1 string totals 10.2 Volts for forward led voltage, the other 16.2 Volts.  The current maximum is set for 12 mA for each ISET.  The enables are PWM's at 30 KHz.  Duty is from 2 to <50 percent.  I realize the 2% duty is below the minimum specification, but that should only affect the linearity if brightness.  It so happens that running at this duty cycle for a few days blows the channel FET and sometimes the switch FET.  Unfortunately this causes a very low resistance from battery to ground and will fry the board traces with no battery-safety enabled.

    Question - Will running a channel at a very low frequency damage the chip?

    Bryan

  • 0 in reply to Bryan Ware91
    Prodigy 50 points
    Question s/b - Will running a channel at very low duty cycle damage the chip?
  • 0
    TI__Intellectual 2140 points
    Hi,

    I would think that the TPS61151 should not die under these conditions. I need to collect some information from the original design team before I can comment on any potential reasons.
    I would not add a R-C from SW to GND because this may slow down the NFET transitions too much and it may cause other problems. I need to confirm that with the IC designers. Also, efficiency will be impacted since the cap has to be charged and discharged between VOUT and GND on every cycle.

    Best Regards,
    Angelos Tsiros
  • 0 in reply to Angelos Tsiros
    TI__Intellectual 2140 points

    Also, the efficiency loss would be much higher due to the I2R losses across the R if an RC is used. A small capacitor between SW and ground would be enough to minimize spikes but I still would not recommend it for the reasons I mentioned in previous reply.

    Best Regards,

    Angelos tsiros