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TPS40210 MOSFET over heating

Other Parts Discussed in Thread: TPS40210, CSD19533Q5A, LM5122, CSD19534Q5A

I am using the TPS40210 as a 81V boost circuit. I have used Webench Buck / Boost circuits many time with no problems. But this one is giving me trouble.

The MOSFET is running hot, even with no load. At 100ma load it heats up enough to melt the solder joint. I started with a TI CSD19533Q5A MOSFET Rds ~ 8mohm, then switched to a Toshiba TPW4R50ANH Rds <4mohm.

Toshiba is running noticeably cooler but still way to hot.

The gate drive looks good at just over 8V (internal 8V LDO), but the drain (while switched on) is still hovering at around 2V. I expect this to be much closer to 0. The source is at zero. I must be missing something. Why am I not slamming the FET on all the way to gnd?

  • Hi John,

    My first suspicion is the series GDRV resistor is limiting the turn on speed too much. This could be checked by measuring the voltage at both sides of the resistor when it turns on the MOSFET. You may see a voltage drop across the resistor as the TPS40210 tries to turn on the MOSFET. Could you try making this 0 ohms to see if there is any improvement?

    Also if you still have it, could you send the report for the WEBENCH circuit you based your design on?

    Best Regards,
    Anthony

  • I have tried shorting the gate resistor, no change.webench_design_16221_33_702190612.pdf

  • Still having serious MOSFET over heating issues.

     

    I have tried ...

    several different MOSFETs (different packages / different manufactures)

    different inductors

    different gate resistance 0 - 20 ohm

    transistor gate buffer

     

    At first I thought it was from the drain only being driven down to 2V, not closer to gnd.

    See screen Rigol capture. Now not even sure that's real ... see Tektronix capture.

     

    Now wondering about the spike on the gate. It is only present under load. Could this be the source of my overheating? some kind of miller coupling?

     

    Any suggestions are appreciated.

    Drain:

    Drain: (old school) looks like .5V, not 2V Rigol shows

    Gate on top / drain on bottom:

  • Thank you for providing the further details on this. Since it looks like the MOSFET is getting turned on correctly and it may have just been an error in the measurement, the next thing to check is the PCB layout. I don't see anything obvious which could be causing this after looking over the schematic and WEBENCH design.

    Two specific things I'm looking to check on the layout are:

    1. How much copper area the pad of the MOSFET is soldered down to
    2. The placement of the components in the critical switching loop. The critical switching loop is through the MOSFET, schottky diode, output capacitor and current sense resistor.

  • I am currently using the eval PCB for prototyping.
    It overheats so extremely, and at very low loads (100ma), I just don't understand it.
    Is it not as simple as P = I * I * Rdson ?

    http://www.ti.com/lit/ds/symlink/tps40210.pdf

  • One thing about the EVM pcb layout is it doesn't have the right footprint for this MOSFET. Is the pad soldered down or are just the pins connected? If the pad isn't soldered down it could reduce the thermal performance.

    The conduction loss in the MOSFET is I*I*Rdson*D, where I is approximately the input current. In addition to the conduction loss, another power loss in the MOSFET is the switching loss each time it turns on and off. If this power loss is what is causing the overheating it could be reduced by lowering the switching frequency. As a test can you try reducing the switching frequency to about 300k by changing RRC to 549kΩ?

  • The part is soldered down, the pins actually align right up with the SOIC layout. I have also tried a few 100V SOIC fets as well.
    All seem to behave the same. I will try reducing the frequency as you suggest.
    What is the "D" you are referring to?

    Thanks for the suggestion.
  • Having the drain pad soldered down is important for the thermal performance. The FETs in the SOIC package are probably rated for less power too because they do not have a pad.

    D is the duty cycle. For a boost it is estimated by (Vout-Vin)/Vout.
  • Anthony - I decreased the frequency to 300KHz as you suggested. That has helped. At 500KHz the solder would melt at 100ma load, now it is almost 300ma. I still believe I am dissipating significantly more wattage than I expect / math suggest.

     

    Can you please call to discuss? 614-451-5646. If I don't get this under control today I will have to switch approach tomorrow.

  • Hi John,

    I believe there is a combination of two things going on here.

    First I think soldering not fully soldering down the pad of the MOSFET is hurting the thermal performance a lot. For example if you compare the TJA of the SOIC MOSFET from the EVM and the CSD19533Q5A, it is 85 deg C/W vs 50 deg C/W respectively. This means the SOIC package may have 70% higher junction temperature than the SON package. Without the pad of the CSD19533Q5A soldered down the thermal performance may end up being more similar to that of the SOIC MOSFET. So if the MOSFET is heating up to 150 deg C now, with the pad fully soldered down the temperature may reduce closer to 90 deg C.

    Second WEBENCH may be underestimating the switching loss in the MOSFET in this design. I am checking with their team how this is calculated and need to wait for their input. The switching frequency will probably need to be kept at 300 kHz or 200 kHz to keep this loss lower.

    You will also probably want to keep the series GDRV resistor at 0 Ohms to make sure the MOSFET can switch as fast as possible to minimize the switching losses.

    Best Regards,
    Anthony

  • Anthony - I think I am getting good thermal contact between the SON package and the PCB. I have Metcal Talons here to easily swap fets. Also when the fet overheats the solder melts and easily reflows under the part. I have also tried some larger parts as well.

    Regardless my math is only showing <1W max. I don't think that should be too much to handle even with a limited thermal connection.
    Can you check my math?
  • As I dig into this more I am becoming more certain there is an issue with the equation for the switching loss.

    The switching loss is estimated by 0.5*Vout*(Tr+Tf)*Iin*fsw. Tr and Tf are the rise times and fall times at the switching node. To get only 0.24 W the rise times and fall times would need to be about 1ns each. This is not realistic. They are probably closer to at least 10ns which puts the switching loss at 2.4W.

    To get the real power loss it would be a useful data point to measure the rise time and fall time at the SW node, using the maximum bandwidth for the oscilloscope. If you find these are 20 ns or longer the TPS40210 driver alone may not be enough to drive the MOSFET needed for this application at this frequency. A lower switching frequency is definitely needed and adding an NPN-PNP to the gate driver like is used in this schematic may give the driver enough strength. Alternatively a controller with a stronger driver like the LM5122 may be needed.

    I'm going to continue to look into the WEBENCH equation to make sure we have the right one in there and make any corrections needed.

  • A MOSFET like the CSD19534Q5A could also operate a lower temperature. It has a smaller gate charge and should have lower switching losses at the trade off of higher Rdson. The decrease in switching loss will be larger than the increase in conduction loss. I estimate the loss will drop by about 500 mW.
  • On your measurement shot of the gate and Drain, one thing looks really suspicious.

    When the gate turns off Drain took quite a while(almost 100ns) to go to 80V, which means the gate is semi-off and burns significant amount of energy. While when it turns on, it takes about 10ns which makes a whole lot more sense.

    For boost topology what you would expect is when the gates truly turns off, you should see the voltage at drain shoot up fast due to the property of the inductor.

    During the semi-off time the current in the inductor is still pouring through the mosfet yet the Rmosfet is so large that you are seeing a lot more power drain than you should.

    When you reduce the frequency, of course you are gonna see the situation improve since it is happening less often.

    So I don't agree that the waveforms are normal, nor do I agree it has any relation to do with Mosfet layout footprint.

    There is significant problem with the operation of the DC/DC converter, although I don't have enough information to determine what went wrong. But one thing is for sure, the turn on and turn off edge should be fairly similar when it functions properly and should be significantly less than 100ns.
  • Also, the gate/drain measurement are out of phase for some reason, since at the kink of the falling end of the gate signal, it indicates hall effect, at which you should see a significant transition of Rmosfet, and you should see a significant dv=Ldi/dt. Not seeing the proper dv indicates that Rmosfet is still quite low(thus the Vdrain is still at GND), then after a while we start to see the ugly 100ns Rmosfet transition which is causing you the problems.
  • Hi Dan,

    You make some good points.

    A likely reason for the slow 100 ns rise on the drain could be the load current this screenshot was taken at. If this was at no load or light load, the peak current should only be about 0.6 A. This is based on 12V input, 33uH inductor, 500 kHz fsw and 80% duty cycle based on the screenshot. Assuming the current is DC, it would take about 55 ns to charge the 400pF capacitance from the CSD19533Q5A to 80 V. Of course this current is not DC so it could definitely take longer.

    However if this was not taken at no load the slow rise time does look very suspect.

    Best Regards,
    Anthony

  • Hi Anthony:

    Just before the Mosfet is turned on again, the Vdrain remains at a steady 80V which tells us that I_L is still not zero.
    So I think the assumption that I_Lmax is 0.6A (I think you derived that from 1.5us*(12/33uH)) is not the case for the measurement.

    I guess OP can answer this question(at 80V ?mA load was the waveforms captured), and we can start from there.

    If it was captured at 80V 100mA as he mentioned several time then the I_Lmax should be close to 1.4A and I_L min should be close to 0.8A.


    Regards.
  • I wanted to give a small update to this. At the beginning of last week we found the error in WEBENCH where the switching loss was incorrectly not being included for the TPS40210. We are in the process of implementing the fix then verifying the efficiency curve matches real designs. I'm very sorry for the troubles this caused.

  • No worries. I was only involved with the discussion as an exercise.

    From the diagram that OP provided, it is fairly evident switching loss is quite substantial.

    Regards.

  • Thanks Anthony,

    I just received my bare PCBs today. I will be assembling in the morning.

    I have several paper designs, assume you would recommend starting with the one that has the lowest switching frequency?

    I have a couple @ 200KHz. I also laid out the board to accept 4 different MOSFET footprints, so I have options.

    John

  •  

    I still am not having any success.

     

    In addition to the switching losses, I am seeing other problems with the Webench results. The frequency is not correct, although measured results are consistent with the charts in the data sheet. Also the part never successfully starts with the Webench Soft Start calculated capacitance. Required capacitance is more in the ball park of .2MF (as the eval board documentation recommends).

     

    I have 2 circuits on this board. The first is a 12V to 27V boost and it works great. Barley warm to the touch at 1A load (27W) out.

     

    The 12V to 81V I cannot get to work at any reasonable temperature to save my live. I have tried reducing the frequency from 500KHz to 350KHz, then to 200KHz. I have a Micrel MOSFET driver to boost my gate drive to 12V. I have decreased the gate turn on time (shorted gate resistor) as well as slowed it down to reduce the ringing. I have even tried a schottky diode in parallel with the gate resistor to allow faster turn off.

     

    Even at very low loads the MOSFET overheats. Almost 50% of the power in is not making it to the load. This must be the heat I am seeing.

     

    The MOSFET duty cycle is much larger than I expected (just gut, not math) at around 75%. But this does appear to be consistent with the scope captures in the data sheet. Just wondering if the inductor is getting saturated and this is raw DC thought the MOSFET.

  • Hi John,

    If you have any spare assembled boards available and you wouldn't mind shipping one here, I can take a look over it on our lab. Let me know.

    I'm also looking through the details closer and will follow up with another post. I can also give you a call to discuss after I review.

    Best Regards,
    Anthonoy

  • Anthony,

     I do not currently have any extra boards. I have only built one (so far) to test and prove out the circuit. I could build another, but I am already behind schedule. Before I built my board I was changing component values on the eval board and was not able to get that working either.

     I think the inductor is getting saturated, and depleting, there is no saw tooth waveform at the switch node. I'm not sure I trust any results generated by webench for this part. Perhaps I should go old school and do the math the long way.

    Please call today. 614-451-5646