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LM3671MF-3.3 Output Short Circuit

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Replies: 17

Views: 2397


We use the LM3671MF-3.3 in a design that has shipped around 2000 units. I have recently had three boards fail with the output of the LM3671MF-3.3 a low resistance (0.5 to 3 ohms). After swapping just this part the board is functional again.

Prior to swapping I checked for solder joint issues or visible damage elsewhere. To be sure I reflowed the joints and retested but in this case the output seems shorted and the power supply does not start up despite 5V on the input.

In this design I have enable tied to VIN which I found is not recommended (I have another post asking about the risks of this). However I have performed full load step tests, power on/off tests, steady full load tests and current limit tests and the part seems to maintain regulation and function within expected limits.

As this is a synchronous design I am wondering if this could be a failure of the rectifier FET.

I wondered if anyone could possibly provide some insight into what could cause the switch node to be near short circuit to 0V.

I had a thought about whether there was a chance the 3.3V switch node could be powered while the input 5V supply was off but I cannot see this in measurement or studying the design. Is it worth adding a diode from output to input (I guess the internal PFET has one) in such designs to make sure power on the output bypasses the device?

Thanks in advance, Mark

17 Replies

  • Hi Mark, as you mentioned connect the en pin to VIn is not recommended in the datasheet, but I don't believe it can cause the SW node short to GND, which means the internal FET is damaged, normally this happens due to EOS event, you can submit these parts through TI quality return for more detail information.
  • In reply to Sheng Jin:

    Thank you for your reply.

    I have been reading up on failure modes of smps mosfets. One thing I need to check is the switch node ringing level to make sure the low side  synchronous fet is not being over stressed.

    I may need to add a snubber circuit to dampen this. The layout is very tight with wide traces and all components  close to the IC so little more I can do to reduce parasitics.

    I have added a voltage detector to set enable high only when vin is greater than 3.0V. I was worried that enabling the part below its minimum voltage may cause shoot through damaging the low side fed.

  • In reply to Mark Williams:

    The maximum voltage on the switch node is listed as vin+0.2V. I assume the body diode of the high side fet would effectively clamp any ringing?

    Could you let me know what the switch node voltage should be limited to? I.e. What is the maximum safe voltage of the low side mosfet to prevent EOS damage?

    Thanks, mark
  • In reply to Mark Williams:

    VIN+0.2V max at according to datasheet.
  • In reply to Sheng Jin:

    Hi Sheng,

    To me that sounds more like the fact that exceeding VIN+0.2V would forward bias the diode in the high-side switch?

    Surely being a synchronous converter there will inevitably be some ringing at the switch node in any design.

    Does the internal synchronous N-FET have an absolute voltage breakdown to know what to limit that ringing to in order to be safe?

  • In reply to Mark Williams:

    For reference the switch node waveforms are shown below. The ringing does exceed VIN+0.2V - I am sure this won't be the EOS level of the FET (why only design in 0.2V margin to breakdown?!). But I do need to know if this needs suppressing with a snubber.

    Note this was measured with short ground clip but only a 200MHz bandwidth scope and 16pF probe. Always difficult to know the true ringing level when themeasurement setup could be affecting it.


    Overshoot to 5.92V, undershoot down to -2.84V.

    Could you let me know if this is a design risk and any recommendations for mitigation?


  • In reply to Mark Williams:

    Any news on the maximum switch pin voltage? I can't believe the low side fet is damaged at vin+0.2V, it must have a higher breakdown.

    synchronous converters are likely to have some switch node ringing caused by layout parasitics. My current layout is tight around the IC with short wide copper pour traces

    I could possibly add a snubber but I would have to move the inductor and output cap further from the switch node which seems counter productive.

    Thanks, mark

  • In reply to Mark Williams:

    sorry for late reply, I agreed the breakdown voltage should be much higher, and the duration is such short in your scope plot. But I am checking with our design for more informaiton.
  • In reply to Sheng Jin:

    Just FYI...

    Usually the dc voltage abs max comes directly from the process specification. Real life switch mode power supplies will always have over shoot and undershoot like you observe. Some datasheets have additional transient short term specification added. Very typical is -3V for 10 or 20 nsec.

    Best  Regards,

    John Tucker

    BSR-MV DC/DC Applications


    “Working on an automotive power design? Read the E2E technical article Meet European Commission ADAS requirements with TI DC/DC for device recommendations and other helpful resources.”


  • In reply to JohnTucker:

    Hi Guys,Here is input from our design:
    Duration of the spike is ok ~10ns so that is not the problem. I don’t also see a problem with the positive excursion as the spike duration is so short. There is however a problem with the undershoot. -2.5V negative spike is way too big and can damage the NMOS body diode. It is, however, impossible to say which spike is the reason for the damage without FA.
    One thing to note. If this is a bonded version of the LM3671, internal spikes can be much higher than what can be measured at the pin.

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