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TPS659037 Boot1 Pin

Nathan Rabenold
Intellectual 745 points
Other Parts Discussed in Thread: TPS659037

Hi-

In looking at the TPS659037 documentation , it is clear that the Boot1 pin being set HIGH sets the Power On Acknowledge Mode to POWERHOLD and allows me to gate the power on sequence through use of the POWERHOLD pin (i.e., POWERHOLD will serve as my "on request").

It is also clear from the documentation that setting Boot1=1 will result in RESET_OUT being asserted during a warm reset.  This is also desired in my design.

The confusion arises in a note on the AM57x EVM schematic that states for Boot1=1, "Double PORz release at startup" and for Boot1=0,"Single PORz release at startup."  It is not clear from the PMIC documentation what this is referring to.  Can you offer any insight into what this note means?

I have designed my board to utilize the Boot1=1 features of the device (POWERHOLD mode and RESET_OUT assertion), but I want to make sure I understand the full functional impact of setting the Boot1 pin in this manner.

Thank you for your assistance,

Nate

  • 0
    TI__Genius 16410 points
    Hello Nathan,

    In a previous revision of the OTP, BOOT1=1 set a RESET_OUT pulse (connected to PORz on the processor) both during start-up and during warm reset. However, the pulse during start-up is no longer required, and has since been removed so that BOOT1=1 only generates a RESET_OUT pulse during warm reset. That note is referring to the pulse during start-up, and can be ignored.

    The full function of BOOT1=1 is the RESET_OUT pulse being generated during the warm reset.

    Regards,
    Karl