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CC(constant current) charging mode, VSYS =3.97, VBAT=3.72V while DLIN=100mV for TWL6032A2B4 with powerpath and hardware controlled charging

Other Parts Discussed in Thread: TWL6032

 we use 580mH LI-Ion battery,  when VBAT=3.7V, the system is on, then we plug in the USB charger

 we set CIN_LIMIT=600mA, VOREG=4.2V and change CHRG_DET_N=1,

our VBAT_HI_MIN =3.4V, so we expect the  TWL6032 will  use  CC(constant current) mode to charge the battery,  and VSYS=VBAT+100mV=3.8V (DLIN=100mV),

but  after measuring by voltage meter,we have seen VBAT=3.7V,VSYS=3.97V, the detla is 270mV,

any parameter I need change to make VSYS track VBAT voltage by 100mV?

  • Hi Charlie,

    What FET are you using for S1 (between VSYS and VBAT)? If it has high resistance that could explain the larger than expected DLIN value possibly. If you modify the VICHRG to a lower value, does the DLIN change? Do you see any LINEAR_CHRG_STS bits being set during this? Section 4.9.3.1 of datasheet has a good explanation of these bits.
  • HI Kevin:
    we use the same PMOS as the reference design CSD25201W15, from the datasheet it can handle 20V, It should be very reliable.
    we cannot see the change when we change VICHRG, from figure4-11, we can see VICHRG will regulate the S1(LDO) current, I cannot find how CHARGERUSB_CTRLIMIT2 can be used,is it like the BUCK_HSLIMI? what is the funciton for CHARGERUSB_CTRLIMIT2 the current limit will do?
    what is the value we should set CHARGERUSB_CTRLLIMIT2? should we always set to the same as VICHRG?
  • Hi Charlie,

    The LIMIT registers can be considered as redundant fail-safe thresholds, configured for the maximum acceptable charging current. By locking these registers the system can prevent future software access from accidentally configuring a dangerous charge current.

    Do you see any change in the behavior when you vary the DLIN value?
  • after change DLIN=200mV, the VSYS-VBAT is under control now, look like 100mV cannot not meet.