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TPS2320 Power on sequence

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Replies: 7

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Does TPS2320 have power on sequence requirement? For example IN1 should be added at first etc....

Now our customer is using channel1 is 12V line and channel2 is 5V line. They done 2 kinds of test as a following,

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Output of channel2 is shorted to GND condition,

1, 12V of channel1 is added  at first, next 5V of channel2 is added. Then channel2 FET becomes off by detecting OC.
2, 12V and 5V are added at same timing. Then TPS2320 is destroyed.
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Do you have any idea for this cause?

Best Regards,
Kohei Sasaki

7 Replies

  • Hi Kohei,

    In general, it should be safer to power IN1 first because that is the rail which powers the internal bias circuitry of the IC. The block diagram on page 2 shows that VREG is powered from IN1. This is mentioned in the VREG description as well on page 3.


    I am unaware of power on sequence requirements but the primary engineer who supports this device will return to the office next week. Once we have some time to discuss with our team and know more, we can offer better suggestions or advice.

    Thanks!
    Alex

    _____________________________________________

    To find the latest information on Power Switches, visit www.ti.com/powerswitch

  • In reply to Alex Triano:

    Alex-san,

    Thank you for your support.
    I'm waiting for further information.

    Best Regards,
    Kohei Sasaki

  • In reply to K. Sasaki14:

    Alex-san,

    Sorry for pushing you.
    However our customer requires prompt information, so could you reply until the end of tomorrow?

    Best Regards,
    Kohei Sasaki

  • In reply to K. Sasaki14:

    HI Kohei,

    Sorry for the delay, have been on a long overseas trip so behind a bit.

    I believe I answered this in a past E2E and will search the archives to give an accruate answer. I recall that IN1 needs to be powered first as Alex notes it provides the PreReg Bias but let me be more thorough in the answer and be sure of the accuracy of it. I can get this tomorrow.

    Brian
  • In reply to Brian Daugherty:

    Brian-san,

    Thank you for your support. 
    If there is requirement that IN1 should be added at first, please let me know the reason and what will happen when the requirement is not met.

    And I have additional question.
    Is there any possibility that other channel side is damaged at the same time when one channel side is damaged by EOS?
    I think there is no possibility if device internal circuit of each channel is independent each other. 

    Best Regards,
    Kohei Sasaki

  • In reply to K. Sasaki14:

    Kohei

    IN1 provides bias for the entire IC. If IN2 comes up first, the outputs are simply held off until IN1 is present, then normal operation will commence. So there isn't a damage issue if IN2 is 1st, only a no-operation condition until IN1 passes through its UVLO level and internal bias is present. As far as EOS, if IN1 section is damaged, then the obvious answer is both channels will be affected. Since it is one die, any EOS can affect the entire IC so it cannot be said that only one channel will be affected by EOS. Damage is a result of heat and can affect adjacent areas of an IC.

    Brian
  • In reply to Brian Daugherty:

    Brian-san,

    Thank you for your answer.
    And I understood there is no requirement of power up sequence, and EOS can affect both channel.

    Please let me know about current limit operation.
    Timer capacitor is charged after TPS2320 detects over current. At this time, does current keeps increasing until timer capacitor charged up to 0.5V?

    At our customer's test, channel2 5V is added at first with output of channel2 is shorted to GND condition. After that channel1 12V is added.
    Then large ringing occurs on channel2 input. This ringing level is over ABS.
    However the ringing level is small when channel1 12V is added at first.

    Do you have any idea for this cause?

    Best Regards,
    Kohei Sasaki 

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