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CSD17484F4: Evaluation Board

Part Number: CSD17484F4
Other Parts Discussed in Thread: CSD23280F3, TINA-TI, CSD23382F4

Hi,

Do we have any board available for the customer to evaluate our femtoFETs? Particularly the CSD17484F4? They have used the simulation models buy they want to move on to destructive tests. 

Thank you,

Ryan Bishop

  • Ryan, 

    I know we are working on an EVM but I am not sure the status. I would recommend reaching out to Kevin O'Connell directly, the PME. Feel free to loop me in. 

  • Hi Brett,

    Thanks for your quick response. I'll take this request direct.

    Regards,
    Ryan
  • Hello, I am trying to use TI p-channel MOSFET PN# CSD23280F3. I used TINA-TI simulation program,

    By inserting the macro for the TINA-TI spice model as shown in the figure below.  Using 3v supply voltage, and the analysis results shows when both Gate and source are connected (2.66 v at the drain) for the first figure (it should be off?). However, changing the orientation for CSD23280F3 as shown in the second figure (there should be a body diode?), the Voltage at the drain is 1.02mV. In addition, I am trying to see when would be the evaluation board available. 

     Thanks,

  • Jeevan, 

    I know the board is being worked on currently, but I am not sure when it will be available. The idea is to put a variety of N and P-Channel FemtoFETs all on a single board for evaluation. 

    Are you asking why you are seeing 1.02mV on the source? This would be due to the 3.4nA leakage current through the FET when it is turned off, which is is spec with the max guaranteed on the datasheet (25nA at 5V). 

  • Thank you for following up.
    we understand , but we would like to operate similar to the first set up ( first figure) , where the source terminal on the (left), so we can use it as power switch . because we don't want the body diode to conduct when source is lower than the drain.
  • Ok so is the question should the FET be / blocking when the source is higher than the drain? Yes, it will. But when the source is lower than the drain, the diode will conduct. This diode is inherent to the device.
  • Thanks Brett,
    I would like to know the following please:
    For Figure 1 - the VGS is zero but why the FET is still "ON" with 8.8 uA going through?? .
    and for Figure 2 the Vd is greater than Vs and we are expecting body diode is conducting but its not?.
  • Aha! I see your point. It is very possible the diode is backwards in the spice model. Let me check with our modeling team and get back to you. Thanks for bringing this to our attention.
  • Jeevan, 

    You were correct and the spice model on the web had the diode configured backwards. Please use the attached. We are working on updating the model online.  

    Again, thank you for highlighting this to us. 

    CSD23280F3.TSM

  • Hello Brett,

    You welcome and thank you for following up, I did simulate the model that you provided. According to the data sheet for ( CSD17484F4) there is gate to source diode but I am trying to isolate the ( gate to source), and I saw another part (CSD23382F4) that might be more efficient for driving the gate as switch . The other part has back to back gate to source diode as shown below; however, the TINA TI spice model is not available. Is there is any way you can provide me with the TINA spice model so I can simulate it to compare it  with the other part?.  

  • Jeevan,
    I have requested a TINA TI SPICE model for the CSD23382F4 - I'll let you know when I have a schedule for completion.

    Not sure why one wasn't already created.
  • Hello Brett,

    Thank you for following up, I am looking forward to hear from you.

  • I submitted a request to build the model. While the model group only would commit to being done within 2 weeks, I was told the time was usually shorter for a FET, so hope to get back to you soon.