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UCC28740: [Layout]: What to do with the ground plane on an isolated SMPS design

Part Number: UCC28740
Other Parts Discussed in Thread: TIDA-00702,

Hello black magic wizards.

I have seen a lot of application notes concerning layout guidelines for switch mode power supplies. Most of them based on a 2 layers PCB stackup.

In our design we will be using a 4 layers PCB stackup, the board also has a digital circuitry based on a TM4C MCU.

The SMPS we are using is similar to the primary side of the one found on TIDA-00702. We want to follow best EMC practices and guidelines.

For minimizing EMI what should we do about the ground plane layer, from what I know splitting the ground plane generates high EMI:

  • Remove the ground plane completely under the SMPS (before isolation) part of the circuit
  • Divide the board ground plane to 2 copper shapes, one under the SMPS (before isolation) connected to neutral (or should it be earth ?). Another under the digital (isolated) section connected to DC ground.
  • Separate the PCB boards. Have one with two layers for the SMPS and another one 4 layers for the digital with power wires running from one to another.

Thanks

  • Hello LazyHD,

    There is no need to break the design into separate PCBs, however it will be wise to split the ground plane (and the other inner-layer associated power plane) into separate regions for both EMI and safety reasons. Splitting a ground plane does not necessarily generate high EMI; the trick is in knowing where to split and where not to split. Depending on circumstances, a judicious split in the right place can also reduce EMI. There are many sources of advice on EMI reduction for pcb layouts, with and without planes, on the internet and within TI. Here are two papers that may help you: www.ti.com/.../snva638a.pdf and www.ti.com/.../szza009.pdf , the former a little more specific to DC/DC converters and logic, and the latter being more generalized.

    Bringing the subject back to your specific implementation, the MCU region after the isolation will benefit from the power and ground planes, following the guidelines mentioned above. However, the primary side of the SPMS needs special consideration not only for EMI suppression, but also from a safety-spacing perspective. Power and GND planes can be beneficial here, too, but are subject to Safety Agency clearance and creepage requirements spelled out in their controlling documents. Perhaps the most recognizable example is IEC-60950 (for IT equipment), which has been adopted more or less verbatim by nearly every national agency. But this is for example only and not to imply that this standard is the correct standard which applies to your project. The main point of this is that any safety spacing requirements may supersede or modify plans you may have for using the planes for EMI reduction in the primary-side region(s) of the SMPS.

    That said, any plane beneath switching nodes and networks, whether signal or power, establish a capacitance to that network. The dv/dt of the signal then generates a current through this capacitance into the plane and circulates back to the source of the signal to complete a current loop. Plane splits and partial splits can serve to contain and steer this current along desired paths to minimize loop-area and radiated-EMI, and to prevent the current(s) from coupling into other noise-sensitive signals.

    Note that I haven’t referred to that plane as specifically GND or power, or any other node, since you can chose which node can be used as a localized reference plane for various purposes. Most likely, at least one primary-side plane will be tied to primary-side return, or PGND, which is not the same as the secondary GND or SGND. It may seem like a good idea to run PGND under the entire primary switching section, control and all, but that is not necessarily a good thing. Switching signals into the UCC28740 controller, like VS, depend on maintaining high-frequency characteristics which the controller senses. The filtering effect of capacitance to PGND can distort those characteristics and may adversely affect control, though maybe not in an obvious manner. PGND running under the drain pad of a surface mount switching MOSFET will increase the effective switched-node capacitance which increases switching loss. In some other areas, the relatively “quiet” FB signal can benefit from PGND shielding, provided that portion of the PGND does not contain switching currents from the PWM section. You have to know what currents are in your planes, and what paths they take. Do not connect to Earth-GND a plane which runs under any part of a switching network or power stage, since it will surely conduct switching currents to Earth, and since those currents have to complete a loop, the noise will come back through the AC lines and/or the output and result in high conducted and radiated EMI.

    At minimum, you can choose to apply the secondary power and GND planes only after the isolation and have no planes in the SMPS area. This approximates a 2-board approach with a single board. Hopefully, the two papers will help you apply plane splits to your benefit on both sides of the isolation boundary.

    Regards,
    Ulrich