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UCC27200A: Bootstrap capacitor value

Hirotsugu Kobayashi
Mastermind 8485 points
Part Number: UCC27200A
Other Parts Discussed in Thread: UCC27210

Hi, team.

Please tell me the way of calculation of the most suitable capacitance value of a boot strap capacitor when using UCC27200A the 80ms cycle and 50% duty.

Best Regards,

  • 0
    TI__Intellectual 2805 points

    Hi Hirotsugu,

    In order to calculate the bootstrap capacitor we would need more information about the design.
    Most of our gate driver datasheet's have a detailed design procedure for calculating bootstrap capacitors.

    Please use the detailed design procedure 8.2.2 in http://www.ti.com/lit/ds/symlink/lm5109b-q1.pdf to calculate the bootstrap capacitor.

    Also, as a general rule the local V_DD bypass capacitor should be 10 times greater than the value of C_Boot. The bootstrap and bias capacitors should be ceramic with XR7 dielectric. The voltage rating should be twice that of the maximum V_DD considering capacitance tolerances once the devices have a DC bias voltage across them and to ensure long-term reliability.

    Regards,
    Mateo

  • 0
    TI__Mastermind 20950 points

     Hello Hirotsugu,

    Thank you for the interest in the UCC27200A for your design. I am an application engineer with TI and will work to support your questions.

    With such a low operating frequency, the bootstrap bias current is the major consideration ins sizing the boot strap capacitor. To calculate the boot strap capacitor use the following formulas.

    Qtotal=Qg +IHB/Fsw, for the UCC27200A IHB is 0.8mA So for a 50nC FET example Qtotal=50nC +0.8mA/12.5Hz=64.04uC.

    For Cboot; Cboot=Qtotal/0.5V (for 0.5V ripple on boot cap), Cboot=64.4uC/0.5V=128uF This is a very large boot capacitor.


    For this application the best choice will be the UCC27210 which has IHB current of 0.1mA. This will result in a boot capacitor 8x smaller, or 16uF.

    If this answers your questions please confirm on the E2E thread.

    Regards,

    Richard Herring

  • 0 in reply to Richard Herring
    Mastermind 8485 points
    Hi, Richard.
    Thank you for your answer.
    But I have one more question, why is the 0.5V used for calculation?
  • 0 in reply to Hirotsugu Kobayashi
    TI__Intellectual 2805 points
    Hi Hirotsugu,

    I believe he is suggesting 0.5V as the maximum allowable voltage drop across the bootstrap capacitor.

    regards,
    Mateo
  • 0 in reply to Mateo Begue
    Mastermind 8485 points
    Hi, team.
    Can the capacity be reduced by putting resistance in a series?
    The speed isn't necessary, so I'm thinking when leakage current can be reduced.

    BR
  • 0 in reply to Hirotsugu Kobayashi
    TI__Mastermind 20950 points

    Hello Hirotsugu,

    Placing a resistance in series of the Mosfet gate will slow down the VGS rise time, but does not reduce the gate drive energy required, and it does not reduce the HB to HS leakage current.

    There was a previous question if the 0.5V ripple voltage can be increased to a higher value, 1.0V for example. We recommend 0.5V as a guideline to ensure that the boot capacitor is fully charged during the low side on time, and that the boot capacitor charging current is not excessive on every switching cycle.

    If indeed the duty cycle is 50% and the low side FET is on for 50% of the time, the ripple voltage likely can be increased since there will be 40ms time to charge the boot capacitor. 

    Regards

    Richard Herring